1 #include <device/device.h>
2 #include <device/pci.h>
3 #include <device/pci_ops.h>
4 #include <device/pci_ids.h>
5 #include <console/console.h>
8 static void ide_init(struct device *dev)
10 struct southbridge_via_vt8235_config *conf = dev->chip_info;
11 unsigned char enables;
13 printk(BIOS_INFO, "Enabling VIA IDE.\n");
15 /*if (!conf->enable_native_ide) { */
17 * Run the IDE controller in 'compatiblity mode - i.e. don't
18 * use PCI interrupts. Using PCI ints confuses linux for some
21 printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n",
23 enables = pci_read_config8(dev, 0x42);
24 printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
25 enables &= ~0xc0; // compatability mode
26 pci_write_config8(dev, 0x42, enables);
27 enables = pci_read_config8(dev, 0x42);
28 printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
32 enables = pci_read_config8(dev, 0x40);
33 printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
35 pci_write_config8(dev, 0x40, enables);
36 enables = pci_read_config8(dev, 0x40);
37 printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
39 // Enable prefetch buffers
40 enables = pci_read_config8(dev, 0x41);
42 pci_write_config8(dev, 0x41, enables);
44 // Lower thresholds (cause award does it)
45 enables = pci_read_config8(dev, 0x43);
48 pci_write_config8(dev, 0x43, enables);
50 // PIO read prefetch counter (cause award does it)
51 pci_write_config8(dev, 0x44, 0x18);
53 // Use memory read multiple
54 pci_write_config8(dev, 0x45, 0x1c);
57 // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
58 // kevinh@ispiri.com - the standard linux drivers seem ass slow when
59 // used in native mode - I've changed back to classic
60 enables = pci_read_config8(dev, 0x9);
61 printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
62 // by the book, set the low-order nibble to 0xa.
63 if (conf->enable_native_ide) {
65 // cf/cg silicon needs an 'f' here.
71 pci_write_config8(dev, 0x9, enables);
72 enables = pci_read_config8(dev, 0x9);
73 printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
75 // standard bios sets master bit.
76 enables = pci_read_config8(dev, 0x4);
77 printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
80 // No need for stepping - kevinh@ispiri.com
83 pci_write_config8(dev, 0x4, enables);
84 enables = pci_read_config8(dev, 0x4);
85 printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
87 if (!conf->enable_native_ide) {
88 // Use compatability mode - per award bios
89 pci_write_config32(dev, 0x10, 0x0);
90 pci_write_config32(dev, 0x14, 0x0);
91 pci_write_config32(dev, 0x18, 0x0);
92 pci_write_config32(dev, 0x1c, 0x0);
94 // Force interrupts to use compat mode - just like Award bios
95 pci_write_config8(dev, 0x3d, 0x0);
96 pci_write_config8(dev, 0x3c, 0xff);
100 static struct device_operations ide_ops = {
101 .read_resources = pci_dev_read_resources,
102 .set_resources = pci_dev_set_resources,
103 .enable_resources = pci_dev_enable_resources,
109 static const struct pci_driver northbridge_driver __pci_driver = {
111 .vendor = PCI_VENDOR_ID_VIA,
112 .device = PCI_DEVICE_ID_VIA_82C586_1,