3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
7 #include <console/console.h>
13 void pc_keyboard_init(void);
17 printk_err("NO HARD RESET ON VT8235! FIX ME!\n");
20 static void usb_on(int enable)
24 /* Base 8235 controller */
25 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
26 /* USB controller 1 */
27 device_t dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
28 /* USB controller 2 */
29 device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev1);
30 /* USB controller 2 */
31 device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA,
32 PCI_DEVICE_ID_VIA_82C586_2, dev2);
36 regval = pci_read_config8(dev0, 0x50);
38 pci_write_config8(dev0, 0x50, regval);
43 pci_write_config8(dev1, 0x04, 0x07);
48 pci_write_config8(dev2, 0x04, 0x07);
53 pci_write_config8(dev3, 0x04, 0x07);
58 regval = pci_read_config8(dev0, 0x50);
60 pci_write_config8(dev0, 0x50, regval);
65 pci_write_config8(dev1, 0x3c, 0x00);
66 pci_write_config8(dev1, 0x04, 0x00);
71 pci_write_config8(dev2, 0x3c, 0x00);
72 pci_write_config8(dev2, 0x04, 0x00);
77 pci_write_config8(dev3, 0x3c, 0x00);
78 pci_write_config8(dev3, 0x04, 0x00);
83 static void keyboard_on(void)
87 /* Base 8235 controller */
88 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
89 PCI_DEVICE_ID_VIA_8235, 0);
92 regval = pci_read_config8(dev0, 0x51);
94 /* !!!FIX let's try this */
96 pci_write_config8(dev0, 0x51, regval);
101 static void nvram_on(void)
104 * the VIA 8235 South has a very different nvram setup than the
106 * turn on ProMedia nvram.
107 * TO DO: use the PciWriteByte function here.
111 * kevinh/Ispiri - I don't think this is the correct address/value
112 * intel_conf_writeb(0x80008841, 0xFF);
118 * Enable the ethernet device and turn off stepping (because it is integrated
119 * inside the southbridge)
121 static void ethernet_fixup()
126 printk_info("Ethernet fixup\n");
128 edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
130 printk_debug("Configuring VIA LAN\n");
132 /* We don't need stepping - though the device supports it */
133 byte = pci_read_config8(edev, PCI_COMMAND);
134 byte &= ~PCI_COMMAND_WAIT;
135 pci_write_config8(edev, PCI_COMMAND, byte);
137 printk_debug("VIA LAN not found\n");
142 /* we need to do things in this function so that PCI scan will find
143 * them. One problem here is that we can't use ANY of the new device
144 * stuff. This work here precedes all that.
145 * Fundamental problem with linuxbios V2 architecture.
146 * You can't do pci control in the C code without having done a PCI scan.
147 * But in some cases you need to to pci control in the c code before doing
148 * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
149 * that has functions with the same name but different type signatures
150 * (e.g. device_t). This needs to get fixed. We need low-level pci scans
153 static void vt8235_pci_enable(struct southbridge_via_vt8235_config *conf)
156 unsigned long busdevfn = 0x8000;
157 if (conf->enable_ide) {
158 printk_debug("%s: enabling IDE function\n", __FUNCTION__);
165 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
167 /* taken some liberties - changed irq structures to pins numbers so that it is easier to
168 * change PCI irq assignments without having to change each PCI function individually
171 /* pciIrqs contains the irqs assigned for PCI pins A-D */
172 /* setting will depend on motherboard as irqs can be quite scarce */
173 /* e.g on EPIA-MII, 16 bit CF card wants a dedicated IRQ. A 16 bit card in pcmcia socket */
174 /* may want another - for now only claim 3 interupts for PCI, leaving at least one spare */
176 /* On EPIA-M one could allocated all four irqs to different numbers since there are no cardbus */
180 static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 10 };
182 static const unsigned char usbPins[4] = { 'A','B','C','D'};
183 static const unsigned char enetPins[4] = { 'A','B','C','D'};
184 static const unsigned char slotPins[4] = { 'B','C','D','A'};
185 static const unsigned char firewirePins[4] = { 'B','C','D','A'};
186 static const unsigned char vt8235Pins[4] = { 'A','B','C','D'};
187 static const unsigned char vgaPins[4] = { 'A','B','C','D'};
188 static const unsigned char cbPins[4] = { 'A','B','C','D'};
189 static const unsigned char riserPins[4] = { 'A','B','C','D'};
191 Our IDSEL mappings are as follows
192 PCI slot is AD31 (device 15) (00:14.0)
193 Southbridge is AD28 (device 12) (00:11.0)
195 static unsigned char *pin_to_irq(const unsigned char *pin)
197 static unsigned char Irqs[4];
199 for (i = 0 ; i < 4 ; i++)
200 Irqs[i] = pciIrqs[ pin[i] - 'A' ];
204 static void pci_routing_fixup(void)
208 dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
209 printk_info("%s: dev is %p\n", __FUNCTION__, dev);
211 /* initialize PCI interupts - these assignments depend
212 on the PCB routing of PINTA-D
219 pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
220 pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
221 pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
227 // firewire built into southbridge
228 printk_info("setting firewire\n");
229 pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins) );
231 // Standard usb components
232 printk_info("setting usb\n");
233 pci_assign_irqs(0, 0x10, pin_to_irq(usbPins) );
235 // VT8235 + sound hardware
236 printk_info("setting vt8235\n");
237 pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins) );
239 // Ethernet built into southbridge
240 printk_info("setting ethernet\n");
241 pci_assign_irqs(0, 0x12, pin_to_irq(enetPins) );
244 printk_info("setting vga\n");
245 pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins) );
248 printk_info("setting pci slot\n");
249 pci_assign_irqs(0, 0x14, pin_to_irq(slotPins) );
252 printk_info("setting cardbus slot\n");
253 pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins) );
255 // Via 2 slot riser card 2nd slot
256 printk_info("setting riser slot\n");
257 pci_assign_irqs(0, 0x13, pin_to_irq(riserPins) );
267 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
270 for(i = 0; i < 256; i += 16) {
271 printk_debug("0x%x: ", i);
272 for(j = 0; j < 16; j++) {
273 printk_debug("%02x ", pci_read_config8(dev0, i+j));
282 // set power led to steady now that lxbios has virtually done its job
284 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,0);
286 pci_write_config8(dev0,0x94,0xb0);
290 /* set up the power management capabilities directly into ACPI mode */
291 /* this avoids having to handle any System Management Interrupts (SMI's) which I can't */
292 /* figure out how to do !!!! */
294 void setup_pm(device_t dev0)
298 pci_write_config8(dev0,0x80,0x20);
300 // Set ACPI base address to IO 0x4000
301 pci_write_config16(dev0, 0x88, 0x0401);
304 pci_write_config8(dev0,0x82,0x55);
306 // primary interupt channel
307 pci_write_config16(dev0,0x84,0x30f2);
309 // throttle / stop clock control
310 pci_write_config8(dev0,0x8d,0x18);
312 pci_write_config8(dev0,0x93,0x88);
313 //pci_write_config8(dev0,0x94,0xb0);
314 pci_write_config8(dev0,0x95,0xc0);
315 pci_write_config8(dev0,0x98,0);
316 pci_write_config8(dev0,0x99,0xea);
317 pci_write_config8(dev0,0xe4,0x14);
318 pci_write_config8(dev0,0xe5,0x08);
321 // Enable ACPI access (and setup like award)
322 pci_write_config8(dev0, 0x81, 0x84);
327 outl(0xffffffff,0x430);
335 outl(0xffff7fff,0x448);
341 static void vt8235_init(struct southbridge_via_vt8235_config *conf)
343 unsigned char enables;
349 // to do: use the pcibios_find function here, instead of
350 // hard coding the devfn.
351 // done - kevinh/Ispiri
352 printk_debug("vt8235 init\n");
353 /* Base 8235 controller */
354 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
356 dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
357 /* Power management controller */
358 //devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0);
360 // enable the internal I/O decode
361 enables = pci_read_config8(dev0, 0x6C);
363 pci_write_config8(dev0, 0x6C, enables);
365 // Map 4MB of FLASH into the address space
366 pci_write_config8(dev0, 0x41, 0x7f);
368 // Set bit 6 of 0x40, because Award does it (IO recovery time)
369 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
370 // interrupts can be properly marked as level triggered.
371 enables = pci_read_config8(dev0, 0x40);
373 pci_write_config8(dev0, 0x40, enables);
375 // Set 0x42 to 0xf0 to match Award bios
376 enables = pci_read_config8(dev0, 0x42);
378 pci_write_config8(dev0, 0x42, enables);
381 /* Set 0x58 to 0x03 to match Award */
382 pci_write_config8(dev0, 0x58, 0x03);
384 /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
385 enables = pci_read_config8(dev0, 0x4f);
387 pci_write_config8(dev0, 0x4f, enables);
391 // Set bit 3 of 0x4a, to match award (dummy pci request)
392 enables = pci_read_config8(dev0, 0x4a);
394 pci_write_config8(dev0, 0x4a, enables);
396 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
397 enables = pci_read_config8(dev0, 0x4f);
399 pci_write_config8(dev0, 0x4f, enables);
401 // Set 0x58 to 0x03 to match Award
402 pci_write_config8(dev0, 0x58, 0x03);
404 // enable the ethernet/RTC
406 enables = pci_read_config8(dev0, 0x51);
408 pci_write_config8(dev0, 0x51, enables);
412 /* enable serial irq */
413 pci_write_config8(dev0,0x52,0x9);
416 pci_write_config8(dev0, 0x53, 0x00);
418 /* Use compatability mode - per award bios */
419 pci_write_config32(dev1, 0x10, 0x0);
420 pci_write_config32(dev1, 0x14, 0x0);
421 pci_write_config32(dev1, 0x18, 0x0);
422 pci_write_config32(dev1, 0x1c, 0x0);
425 // Power management setup
432 if (! conf->enable_native_ide) {
433 // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
434 // interrupts. Using PCI ints confuses linux for some reason.
436 printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
437 enables = pci_read_config8(dev1, 0x42);
438 printk_debug("enables in reg 0x42 0x%x\n", enables);
439 enables &= ~0xc0; // compatability mode
440 pci_write_config8(dev1, 0x42, enables);
441 enables = pci_read_config8(dev1, 0x42);
442 printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
445 enables = pci_read_config8(dev1, 0x40);
446 printk_debug("enables in reg 0x40 0x%x\n", enables);
448 pci_write_config8(dev1, 0x40, enables);
449 enables = pci_read_config8(dev1, 0x40);
450 printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
452 // Enable prefetch buffers
453 enables = pci_read_config8(dev1, 0x41);
455 pci_write_config8(dev1, 0x41, enables);
457 // Lower thresholds (cause award does it)
458 enables = pci_read_config8(dev1, 0x43);
461 pci_write_config8(dev1, 0x43, enables);
463 // PIO read prefetch counter (cause award does it)
464 pci_write_config8(dev1, 0x44, 0x18);
466 // Use memory read multiple
467 pci_write_config8(dev1, 0x45, 0x1c);
470 // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
471 // kevinh@ispiri.com - the standard linux drivers seem ass slow when
472 // used in native mode - I've changed back to classic
473 enables = pci_read_config8(dev1, 0x9);
474 printk_debug("enables in reg 0x9 0x%x\n", enables);
475 // by the book, set the low-order nibble to 0xa.
476 if (conf->enable_native_ide) {
478 // cf/cg silicon needs an 'f' here.
484 pci_write_config8(dev1, 0x9, enables);
485 enables = pci_read_config8(dev1, 0x9);
486 printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
488 // standard bios sets master bit.
489 enables = pci_read_config8(dev1, 0x4);
490 printk_debug("command in reg 0x4 0x%x\n", enables);
493 // No need for stepping - kevinh@ispiri.com
496 pci_write_config8(dev1, 0x4, enables);
497 enables = pci_read_config8(dev1, 0x4);
498 printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
500 if (! conf->enable_native_ide) {
501 // Use compatability mode - per award bios
502 pci_write_config32(dev1, 0x10, 0x0);
503 pci_write_config32(dev1, 0x14, 0x0);
504 pci_write_config32(dev1, 0x18, 0x0);
505 pci_write_config32(dev1, 0x1c, 0x0);
507 // Force interrupts to use compat mode - just like Award bios
508 pci_write_config8(dev1, 0x3d, 00);
509 pci_write_config8(dev1, 0x3c, 0xff);
513 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
514 pci_write_config8(dev0, 0x40, 0x54);
523 static void southbridge_init(struct chip *chip, enum chip_pass pass)
526 struct southbridge_via_vt8235_config *conf =
527 (struct southbridge_via_vt8235_config *)chip->chip_info;
530 case CONF_PASS_PRE_PCI:
531 vt8235_pci_enable(conf);
534 case CONF_PASS_POST_PCI:
535 /* initialise the PIC - particularly so that VGA bios init code
536 doesn't get nasty unknown interupt vectors when it tries to establish
549 case CONF_PASS_PRE_BOOT:
560 struct chip_operations southbridge_via_vt8235_control = {
561 CHIP_NAME("VIA vt8235")
562 .enable = southbridge_init,