1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_ids.h>
7 #include <pc80/mc146818rtc.h>
13 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
14 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
15 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
18 Our IDSEL mappings are as follows
19 PCI slot is AD31 (device 15) (00:14.0)
20 Southbridge is AD28 (device 12) (00:11.0)
22 static void pci_routing_fixup(struct device *dev)
25 printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
27 /* initialize PCI interupts - these assignments depend
28 on the PCB routing of PINTA-D
35 pci_write_config8(dev, 0x55, 0xb0);
36 pci_write_config8(dev, 0x56, 0xa5);
37 pci_write_config8(dev, 0x57, 0xc0);
40 // Standard southbridge components
41 printk(BIOS_INFO, "setting southbridge\n");
42 pci_assign_irqs(0, 0x11, southbridgeIrqs);
44 // Ethernet built into southbridge
45 printk(BIOS_INFO, "setting ethernet\n");
46 pci_assign_irqs(0, 0x12, enetIrqs);
49 printk(BIOS_INFO, "setting pci slot\n");
50 pci_assign_irqs(0, 0x14, slotIrqs);
51 printk(BIOS_INFO, "%s: DONE\n", __func__);
54 static void vt8231_init(struct device *dev)
56 unsigned char enables;
58 printk(BIOS_DEBUG, "vt8231 init\n");
60 // enable the internal I/O decode
61 enables = pci_read_config8(dev, 0x6C);
63 pci_write_config8(dev, 0x6C, enables);
65 // Map 4MB of FLASH into the address space
66 pci_write_config8(dev, 0x41, 0x7f);
68 // Set bit 6 of 0x40, because Award does it (IO recovery time)
69 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
70 // interrupts can be properly marked as level triggered.
71 enables = pci_read_config8(dev, 0x40);
72 pci_write_config8(dev, 0x40, enables);
74 // Set 0x42 to 0xf0 to match Award bios
75 enables = pci_read_config8(dev, 0x42);
77 pci_write_config8(dev, 0x42, enables);
79 // Set bit 3 of 0x4a, to match award (dummy pci request)
80 enables = pci_read_config8(dev, 0x4a);
82 pci_write_config8(dev, 0x4a, enables);
84 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
85 enables = pci_read_config8(dev, 0x4f);
87 pci_write_config8(dev, 0x4f, enables);
89 // Set 0x58 to 0x03 to match Award
90 pci_write_config8(dev, 0x58, 0x03);
92 // enable the ethernet/RTC
94 enables = pci_read_config8(dev, 0x51);
96 pci_write_config8(dev, 0x51, enables);
99 // enable IDE, since Linux won't do it.
100 // First do some more things to devfn (17,0)
101 // note: this should already be cleared, according to the book.
102 enables = pci_read_config8(dev, 0x50);
103 printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
104 enables &= ~8; // need manifest constant here!
105 printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
106 pci_write_config8(dev, 0x50, enables);
108 // set default interrupt values (IDE)
109 enables = pci_read_config8(dev, 0x4c);
110 printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
111 // clear out whatever was there.
114 printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
115 pci_write_config8(dev, 0x4c, enables);
117 // set up the serial port interrupts.
118 // com2 to 3, com1 to 4
119 pci_write_config8(dev, 0x46, 0x04);
120 pci_write_config8(dev, 0x47, 0x03);
121 pci_write_config8(dev, 0x6e, 0x98);
123 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
124 pci_write_config8(dev, 0x40, 0x54);
131 static void vt8231_read_resources(device_t dev)
133 struct resource *res;
135 pci_dev_read_resources(dev);
137 res = new_resource(dev, 1);
139 res->size = 0x1000UL;
140 res->limit = 0xffffUL;
141 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
143 res = new_resource(dev, 3); /* IOAPIC */
144 res->base = 0xfec00000;
145 res->size = 0x00001000;
146 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
149 static void southbridge_init(struct device *dev)
152 pci_routing_fixup(dev);
155 static struct device_operations vt8231_lpc_ops = {
156 .read_resources = vt8231_read_resources,
157 .set_resources = pci_dev_set_resources,
158 .enable_resources = pci_dev_enable_resources,
159 .init = &southbridge_init,
160 .scan_bus = scan_static_bus,
165 static const struct pci_driver lpc_driver __pci_driver = {
166 .ops = &vt8231_lpc_ops,
167 .vendor = PCI_VENDOR_ID_VIA,
168 .device = PCI_DEVICE_ID_VIA_8231,