1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_ids.h>
6 #include <pc80/mc146818rtc.h>
7 #include <arch/ioapic.h>
12 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
13 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
14 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
17 Our IDSEL mappings are as follows
18 PCI slot is AD31 (device 15) (00:14.0)
19 Southbridge is AD28 (device 12) (00:11.0)
21 static void pci_routing_fixup(struct device *dev)
24 printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
26 /* initialize PCI interupts - these assignments depend
27 on the PCB routing of PINTA-D
34 pci_write_config8(dev, 0x55, 0xb0);
35 pci_write_config8(dev, 0x56, 0xa5);
36 pci_write_config8(dev, 0x57, 0xc0);
39 // Standard southbridge components
40 printk(BIOS_INFO, "setting southbridge\n");
41 pci_assign_irqs(0, 0x11, southbridgeIrqs);
43 // Ethernet built into southbridge
44 printk(BIOS_INFO, "setting ethernet\n");
45 pci_assign_irqs(0, 0x12, enetIrqs);
48 printk(BIOS_INFO, "setting pci slot\n");
49 pci_assign_irqs(0, 0x14, slotIrqs);
50 printk(BIOS_INFO, "%s: DONE\n", __func__);
53 static void vt8231_init(struct device *dev)
55 unsigned char enables;
57 printk(BIOS_DEBUG, "vt8231 init\n");
59 // enable the internal I/O decode
60 enables = pci_read_config8(dev, 0x6C);
62 pci_write_config8(dev, 0x6C, enables);
64 // Map 4MB of FLASH into the address space
65 pci_write_config8(dev, 0x41, 0x7f);
67 // Set bit 6 of 0x40, because Award does it (IO recovery time)
68 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
69 // interrupts can be properly marked as level triggered.
70 enables = pci_read_config8(dev, 0x40);
71 pci_write_config8(dev, 0x40, enables);
73 // Set 0x42 to 0xf0 to match Award bios
74 enables = pci_read_config8(dev, 0x42);
76 pci_write_config8(dev, 0x42, enables);
78 // Set bit 3 of 0x4a, to match award (dummy pci request)
79 enables = pci_read_config8(dev, 0x4a);
81 pci_write_config8(dev, 0x4a, enables);
83 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
84 enables = pci_read_config8(dev, 0x4f);
86 pci_write_config8(dev, 0x4f, enables);
88 // Set 0x58 to 0x03 to match Award
89 pci_write_config8(dev, 0x58, 0x03);
91 // enable the ethernet/RTC
93 enables = pci_read_config8(dev, 0x51);
95 pci_write_config8(dev, 0x51, enables);
98 // enable IDE, since Linux won't do it.
99 // First do some more things to devfn (17,0)
100 // note: this should already be cleared, according to the book.
101 enables = pci_read_config8(dev, 0x50);
102 printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
103 enables &= ~8; // need manifest constant here!
104 printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
105 pci_write_config8(dev, 0x50, enables);
107 // set default interrupt values (IDE)
108 enables = pci_read_config8(dev, 0x4c);
109 printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
110 // clear out whatever was there.
113 printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
114 pci_write_config8(dev, 0x4c, enables);
116 // set up the serial port interrupts.
117 // com2 to 3, com1 to 4
118 pci_write_config8(dev, 0x46, 0x04);
119 pci_write_config8(dev, 0x47, 0x03);
120 pci_write_config8(dev, 0x6e, 0x98);
122 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
123 pci_write_config8(dev, 0x40, 0x54);
130 static void vt8231_read_resources(device_t dev)
132 struct resource *res;
134 pci_dev_read_resources(dev);
136 res = new_resource(dev, 1);
138 res->size = 0x1000UL;
139 res->limit = 0xffffUL;
140 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
142 res = new_resource(dev, 3); /* IOAPIC */
143 res->base = IO_APIC_ADDR;
144 res->size = 0x00001000;
145 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
148 static void southbridge_init(struct device *dev)
151 pci_routing_fixup(dev);
154 static struct device_operations vt8231_lpc_ops = {
155 .read_resources = vt8231_read_resources,
156 .set_resources = pci_dev_set_resources,
157 .enable_resources = pci_dev_enable_resources,
158 .init = &southbridge_init,
159 .scan_bus = scan_static_bus,
164 static const struct pci_driver lpc_driver __pci_driver = {
165 .ops = &vt8231_lpc_ops,
166 .vendor = PCI_VENDOR_ID_VIA,
167 .device = PCI_DEVICE_ID_VIA_8231,