src/southbridge/via/vt8231/vt8231_ide.c

   1 #include <console/console.h>
   2 #include <device/device.h>
   3 #include <device/pci.h>
   4 #include <device/pci_ops.h>
   5 #include <device/pci_ids.h>
   6 #include "vt8231.h"
   7 #include "chip.h"
   8
   9 static void ide_init(struct device *dev)
  10 {
  11         struct southbridge_via_vt8231_config *conf;
  12         unsigned char enables;
  13
  14         if (!conf->enable_native_ide) {
  15                 // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
  16                 // interrupts.  Using PCI ints confuses linux for some reason.
  17
  18                 printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
  19                 enables = pci_read_config8(dev, 0x42);
  20                 printk_debug("enables in reg 0x42 0x%x\n", enables);
  21                 enables &= ~0xc0;               // compatability mode
  22                 pci_write_config8(dev, 0x42, enables);
  23                 enables = pci_read_config8(dev, 0x42);
  24                 printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
  25         }
  26
  27         enables = pci_read_config8(dev, 0x40);
  28         printk_debug("enables in reg 0x40 0x%x\n", enables);
  29         enables |= 3;
  30         pci_write_config8(dev, 0x40, enables);
  31         enables = pci_read_config8(dev, 0x40);
  32         printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
  33
  34         // Enable prefetch buffers
  35         enables = pci_read_config8(dev, 0x41);
  36         enables |= 0xf0;
  37         pci_write_config8(dev, 0x41, enables);
  38
  39         // Lower thresholds (cause award does it)
  40         enables = pci_read_config8(dev, 0x43);
  41         enables &= ~0x0f;
  42         enables |=  0x05;
  43         pci_write_config8(dev, 0x43, enables);
  44
  45         // PIO read prefetch counter (cause award does it)
  46         pci_write_config8(dev, 0x44, 0x18);
  47
  48         // Use memory read multiple
  49         pci_write_config8(dev, 0x45, 0x1c);
  50
  51         // address decoding.
  52         // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
  53         // kevinh@ispiri.com - the standard linux drivers seem ass slow when
  54         // used in native mode - I've changed back to classic
  55         enables = pci_read_config8(dev, 0x9);
  56         printk_debug("enables in reg 0x9 0x%x\n", enables);
  57         // by the book, set the low-order nibble to 0xa.
  58         if (conf->enable_native_ide) {
  59                 enables &= ~0xf;
  60                 // cf/cg silicon needs an 'f' here.
  61                 enables |= 0xf;
  62         } else {
  63                 enables &= ~0x5;
  64         }
  65
  66         pci_write_config8(dev, 0x9, enables);
  67         enables = pci_read_config8(dev, 0x9);
  68         printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
  69
  70         // standard bios sets master bit.
  71         enables = pci_read_config8(dev, 0x4);
  72         printk_debug("command in reg 0x4 0x%x\n", enables);
  73         enables |= 7;
  74
  75         // No need for stepping - kevinh@ispiri.com
  76         enables &= ~0x80;
  77
  78         pci_write_config8(dev, 0x4, enables);
  79         enables = pci_read_config8(dev, 0x4);
  80         printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
  81
  82         if (!conf->enable_native_ide) {
  83                 // Use compatability mode - per award bios
  84                 pci_write_config32(dev, 0x10, 0x0);
  85                 pci_write_config32(dev, 0x14, 0x0);
  86                 pci_write_config32(dev, 0x18, 0x0);
  87                 pci_write_config32(dev, 0x1c, 0x0);
  88
  89                 // Force interrupts to use compat mode - just like Award bios
  90                 pci_write_config8(dev, 0x3d, 00);
  91                 pci_write_config8(dev, 0x3c, 0xff);
  92         }
  93 }
  94
  95 static struct device_operations ide_ops = {
  96         .read_resources   = pci_dev_read_resources,
  97         .set_resources    = pci_dev_set_resources,
  98         .enable_resources = pci_dev_enable_resources,
  99         .init             = ide_init,
 100         .enable           = 0,
 101         .ops_pci          = 0,
 102 };
 103
 104 static struct pci_driver northbridge_driver __pci_driver = {
 105         .ops    = &ide_ops,
 106         .vendor = PCI_VENDOR_ID_VIA,
 107         .device = PCI_DEVICE_ID_VIA_82C586_1,
 108 };