1 #define SMBUS_IO_BASE 0x5000
12 #define SMBTRNSADD 0x9
13 #define SMBSLVDATA 0xa
14 #define SMLINK_PIN_CTL 0xe
15 #define SMBUS_PIN_CTL 0xf
17 /* Define register settings */
18 #define HOST_RESET 0xff
19 #define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
20 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
23 #define SMBUS_TIMEOUT (100*1000*10)
25 static void enable_smbus(void)
29 /* Power management controller */
30 dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
32 if (dev == PCI_DEV_INVALID) {
33 die("SMBUS controller not found\r\n");
36 // set IO base address to SMBUS_IO_BASE
37 pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
40 c = pci_read_config8(dev, 0xd2);
42 pci_write_config8(dev, 0xd2, c);
44 /* make it work for I/O ...
46 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
47 c = pci_read_config8(dev, 4);
49 pci_write_config8(dev, 4, c);
51 print_debug(" is the comm register\r\n");
53 print_debug("SMBus controller enabled\r\n");
57 static inline void smbus_delay(void)
62 static int smbus_wait_until_ready(void)
66 loops = SMBUS_TIMEOUT;
70 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
75 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
83 void smbus_reset(void)
85 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
86 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
87 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
88 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
90 smbus_wait_until_ready();
91 print_debug("After reset status ");
92 print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
98 static int smbus_wait_until_done(void)
102 loops = SMBUS_TIMEOUT;
107 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
115 static void smbus_print_error(unsigned char host_status_register)
118 print_err("smbus_error: ");
119 print_err_hex8(host_status_register);
121 if (host_status_register & (1 << 4)) {
122 print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
124 if (host_status_register & (1 << 3)) {
125 print_err("Bus Error\r\n");
127 if (host_status_register & (1 << 2)) {
128 print_err("Device Error\r\n");
130 if (host_status_register & (1 << 1)) {
131 print_err("Interrupt/SMI# was Successful Completion\r\n");
133 if (host_status_register & (1 << 0)) {
134 print_err("Host Busy\r\n");
139 /* SMBus routines borrowed from VIA's Trident Driver */
140 /* this works, so I am not going to touch it for now -- rgm */
141 static unsigned char smbus_read_byte(unsigned char devAdr,
142 unsigned char bIndex)
146 unsigned char sts = 0;
148 /* clear host status */
149 outb(0xff, SMBUS_IO_BASE);
151 /* check SMBUS ready */
152 for ( i = 0; i < 0xFFFF; i++ )
153 if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
156 /* set host command */
157 outb(bIndex, SMBUS_IO_BASE+3);
159 /* set slave address */
160 outb(devAdr | 0x01, SMBUS_IO_BASE+4);
163 outb(0x48, SMBUS_IO_BASE+2);
165 /* SMBUS Wait Ready */
166 for ( i = 0; i < 0xFFFF; i++ )
167 if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
169 if ((sts & ~3) != 0) {
170 smbus_print_error(sts);
173 bData=inb(SMBUS_IO_BASE+5);
179 /* for reference, here is the fancier version which we will use at some
183 int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
185 unsigned char host_status_register;
190 smbus_wait_until_ready();
192 /* setup transaction */
193 /* disable interrupts */
194 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
195 /* set the device I'm talking too */
196 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
197 /* set the command/address... */
198 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
199 /* set up for a byte data read */
200 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
201 SMBUS_IO_BASE + SMBHSTCTL);
203 /* clear any lingering errors, so the transaction will run */
204 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
206 /* clear the data byte...*/
207 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
209 /* start the command */
210 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
211 SMBUS_IO_BASE + SMBHSTCTL);
213 /* poll for transaction completion */
214 smbus_wait_until_done();
216 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
218 /* Ignore the In Use Status... */
219 host_status_register &= ~(1 << 6);
221 /* read results of transaction */
222 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
223 smbus_print_error(byte);
226 return host_status_register != 0x02;