1 #define SMBUS_IO_BASE 0x5000
12 #define SMBTRNSADD 0x9
13 #define SMBSLVDATA 0xa
14 #define SMLINK_PIN_CTL 0xe
15 #define SMBUS_PIN_CTL 0xf
17 /* Define register settings */
18 #define HOST_RESET 0xff
19 #define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
20 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
23 #define SMBUS_TIMEOUT (100*1000*10)
25 static void enable_smbus(void)
29 /* Power management controller */
30 dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
32 if (dev == PCI_DEV_INVALID) {
33 die("SMBUS controller not found\r\n");
36 // set IO base address to SMBUS_IO_BASE
37 pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
40 c = pci_read_config8(dev, 0xd2);
42 pci_write_config8(dev, 0xd2, c);
44 c = pci_read_config8(dev, 0x54);
46 pci_write_config8(dev, 0xd2, c);
49 print_debug("SMBus controller enabled\r\n");
53 static inline void smbus_delay(void)
58 static int smbus_wait_until_ready(void)
62 loops = SMBUS_TIMEOUT;
66 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
71 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
79 void smbus_reset(void)
81 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
82 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
83 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
84 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
86 smbus_wait_until_ready();
87 print_err("After reset status ");
88 print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
94 static int smbus_wait_until_done(void)
98 loops = SMBUS_TIMEOUT;
103 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
111 static void smbus_print_error(unsigned char host_status_register)
114 print_err("smbus_error: ");
115 print_err_hex8(host_status_register);
117 if (host_status_register & (1 << 4)) {
118 print_err("Interrup/SMI# was Failed Bus Transaction\n");
120 if (host_status_register & (1 << 3)) {
121 print_err("Bus Error\n");
123 if (host_status_register & (1 << 2)) {
124 print_err("Device Error\n");
126 if (host_status_register & (1 << 1)) {
127 print_err("Interrupt/SMI# was Successful Completion\n");
129 if (host_status_register & (1 << 0)) {
130 print_err("Host Busy\n");
135 /* SMBus routines borrowed from VIA's Trident Driver */
136 /* this works, so I am not going to touch it for now -- rgm */
137 static unsigned char smbus_read_byte(unsigned char devAdr,
138 unsigned char bIndex)
144 /* clear host status */
145 outb(0xff, SMBUS_IO_BASE);
147 /* check SMBUS ready */
148 for ( i = 0; i < 0xFFFF; i++ )
149 if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
152 /* set host command */
153 outb(bIndex, SMBUS_IO_BASE+3);
155 /* set slave address */
156 outb(devAdr | 0x01, SMBUS_IO_BASE+4);
159 outb(0x48, SMBUS_IO_BASE+2);
161 /* SMBUS Wait Ready */
162 for ( i = 0; i < 0xFFFF; i++ )
163 if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
165 if ((sts & ~3) != 0) {
166 smbus_print_error(sts);
169 bData=inb(SMBUS_IO_BASE+5);
175 /* for reference, here is the fancier version which we will use at some
179 int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
181 unsigned char host_status_register;
186 smbus_wait_until_ready();
188 /* setup transaction */
189 /* disable interrupts */
190 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
191 /* set the device I'm talking too */
192 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
193 /* set the command/address... */
194 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
195 /* set up for a byte data read */
196 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
197 SMBUS_IO_BASE + SMBHSTCTL);
199 /* clear any lingering errors, so the transaction will run */
200 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
202 /* clear the data byte...*/
203 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
205 /* start the command */
206 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
207 SMBUS_IO_BASE + SMBHSTCTL);
209 /* poll for transaction completion */
210 smbus_wait_until_done();
212 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
214 /* Ignore the In Use Status... */
215 host_status_register &= ~(1 << 6);
217 /* read results of transaction */
218 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
219 smbus_print_error(byte);
222 return host_status_register != 0x02;