3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
7 #include <device/chip.h>
8 #include <console/console.h>
12 void pc_keyboard_init(void);
16 printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
18 static void usb_on(int enable)
23 /* Base 8231 controller */
24 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
25 PCI_DEVICE_ID_VIA_8231, 0);
26 /* USB controller 1 */
27 device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, \
28 PCI_DEVICE_ID_VIA_82C586_2, 0);
29 /* USB controller 2 */
30 device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, \
31 PCI_DEVICE_ID_VIA_82C586_2, \
37 pci_write_config8(dev2, 0x3c, 0x05);
38 pci_write_config8(dev2, 0x04, 0x07);
40 pci_write_config8(dev2, 0x3c, 0x00);
41 pci_write_config8(dev2, 0x04, 0x00);
46 regval = pci_read_config8(dev0, 0x50);
51 pci_write_config8(dev0, 0x50, regval);
57 pci_write_config8(dev3, 0x3c, 0x05);
58 pci_write_config8(dev3, 0x04, 0x07);
60 pci_write_config8(dev3, 0x3c, 0x00);
61 pci_write_config8(dev3, 0x04, 0x00);
66 regval = pci_read_config8(dev0, 0x50);
71 pci_write_config8(dev0, 0x50, regval);
76 static void keyboard_on()
80 /* Base 8231 controller */
81 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
82 PCI_DEVICE_ID_VIA_8231, 0);
84 /* kevinh/Ispiri - update entire function to use
85 new pci_write_config8 */
88 regval = pci_read_config8(dev0, 0x51);
90 pci_write_config8(dev0, 0x51, regval);
96 static void nvram_on()
99 * the VIA 8231 South has a very different nvram setup than the
101 * turn on ProMedia nvram.
102 * TO DO: use the PciWriteByte function here.
106 * kevinh/Ispiri - I don't think this is the correct address/value
107 * intel_conf_writeb(0x80008841, 0xFF);
113 * Enable the ethernet device and turn off stepping (because it is integrated
114 * inside the southbridge)
116 static void ethernet_fixup()
121 printk_info("Ethernet fixup\n");
123 edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
125 printk_debug("Configuring VIA LAN\n");
127 /* We don't need stepping - though the device supports it */
128 byte = pci_read_config8(edev, PCI_COMMAND);
129 byte &= ~PCI_COMMAND_WAIT;
130 pci_write_config8(edev, PCI_COMMAND, byte);
132 printk_debug("VIA LAN not found\n");
137 /* we need to do things in this function so that PCI scan will find
138 * them. One problem here is that we can't use ANY of the new device
139 * stuff. This work here precedes all that.
140 * Fundamental problem with linuxbios V2 architecture.
141 * You can't do pci control in the C code without having done a PCI scan.
142 * But in some cases you need to to pci control in the c code before doing
143 * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
144 * that has functions with the same name but different type signatures
145 * (e.g. device_t). This needs to get fixed. We need low-level pci scans
148 static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) {
150 unsigned long busdevfn = 0x8000;
151 if (conf->enable_ide) {
152 printk_spew("%s: enabling IDE function\n", __FUNCTION__);
159 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
162 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
163 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
164 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
167 Our IDSEL mappings are as follows
168 PCI slot is AD31 (device 15) (00:14.0)
169 Southbridge is AD28 (device 12) (00:11.0)
171 static void pci_routing_fixup(void)
175 dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
176 printk_info("%s: dev is %p\n", __FUNCTION__, dev);
178 /* initialize PCI interupts - these assignments depend
179 on the PCB routing of PINTA-D
186 pci_write_config8(dev, 0x55, 0xb0);
187 pci_write_config8(dev, 0x56, 0xa5);
188 pci_write_config8(dev, 0x57, 0xc0);
191 // Standard southbridge components
192 printk_info("setting southbridge\n");
193 pci_assign_irqs(0, 0x11, southbridgeIrqs);
195 // Ethernet built into southbridge
196 printk_info("setting ethernet\n");
197 pci_assign_irqs(0, 0x12, enetIrqs);
200 printk_info("setting pci slot\n");
201 pci_assign_irqs(0, 0x14, slotIrqs);
202 printk_info("%s: DONE\n", __FUNCTION__);
207 static void vt8231_init(struct southbridge_via_vt8231_config *conf)
209 unsigned char enables;
214 // to do: use the pcibios_find function here, instead of
215 // hard coding the devfn.
216 // done - kevinh/Ispiri
217 printk_spew("vt8231 init\n");
218 /* Base 8231 controller */
219 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
221 dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \
223 /* Power management controller */
224 devpwr = dev_find_device(PCI_VENDOR_ID_VIA, \
225 PCI_DEVICE_ID_VIA_8231_4, 0);
227 // enable the internal I/O decode
228 enables = pci_read_config8(dev0, 0x6C);
230 pci_write_config8(dev0, 0x6C, enables);
232 // Map 4MB of FLASH into the address space
233 pci_write_config8(dev0, 0x41, 0x7f);
235 // Set bit 6 of 0x40, because Award does it (IO recovery time)
236 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
237 // interrupts can be properly marked as level triggered.
238 enables = pci_read_config8(dev0, 0x40);
239 pci_write_config8(dev0, 0x40, enables);
241 // Set 0x42 to 0xf0 to match Award bios
242 enables = pci_read_config8(dev0, 0x42);
244 pci_write_config8(dev0, 0x42, enables);
246 // Set bit 3 of 0x4a, to match award (dummy pci request)
247 enables = pci_read_config8(dev0, 0x4a);
249 pci_write_config8(dev0, 0x4a, enables);
251 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
252 enables = pci_read_config8(dev0, 0x4f);
254 pci_write_config8(dev0, 0x4f, enables);
256 // Set 0x58 to 0x03 to match Award
257 pci_write_config8(dev0, 0x58, 0x03);
259 // enable the ethernet/RTC
261 enables = pci_read_config8(dev0, 0x51);
263 pci_write_config8(dev0, 0x51, enables);
267 // enable com1 and com2.
268 if (conf->enable_com_ports) {
269 enables = pci_read_config8(dev0, 0x6e);
271 /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
272 * is enable com port a as com1 kevinh/Ispiri - Old code
273 * thought 0x01 would make it com1, that was wrong enables =
274 * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
275 * enables); // note: this is also a redo of some port of
276 * assembly, but we want everything up.
279 /* set com1 to 115 kbaud not clear how to do this yet.
280 * forget it; done in assembly.
284 // enable IDE, since Linux won't do it.
285 // First do some more things to devfn (17,0)
286 // note: this should already be cleared, according to the book.
287 enables = pci_read_config8(dev0, 0x50);
288 printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
289 enables &= ~8; // need manifest constant here!
290 printk_debug("set IDE reg. 50 to 0x%x\n", enables);
291 pci_write_config8(dev0, 0x50, enables);
293 // set default interrupt values (IDE)
294 enables = pci_read_config8(dev0, 0x4c);
295 printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
296 // clear out whatever was there.
299 printk_debug("setting reg. 4c to 0x%x\n", enables);
300 pci_write_config8(dev0, 0x4c, enables);
302 // set up the serial port interrupts.
303 // com2 to 3, com1 to 4
304 pci_write_config8(dev0, 0x46, 0x04);
305 pci_write_config8(dev0, 0x47, 0x03);
308 // Power management setup
310 // Set ACPI base address to IO 0x4000
311 pci_write_config32(devpwr, 0x48, 0x4001);
313 // Enable ACPI access (and setup like award)
314 pci_write_config8(devpwr, 0x41, 0x84);
316 // Set hardware monitor base address to IO 0x6000
317 pci_write_config32(devpwr, 0x70, 0x6001);
319 // Enable hardware monitor (and setup like award)
320 pci_write_config8(devpwr, 0x74, 0x01);
322 // set IO base address to 0x5000
323 pci_write_config32(devpwr, 0x90, 0x5001);
326 pci_write_config8(devpwr, 0xd2, 0x01);
331 if (conf->enable_native_ide) {
332 // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
333 // interrupts. Using PCI ints confuses linux for some reason.
335 printk_info("%s: enabling native IDE addresses\n", __FUNCTION__);
336 enables = pci_read_config8(dev1, 0x42);
337 printk_debug("enables in reg 0x42 0x%x\n", enables);
338 enables &= ~0xc0; // compatability mode
339 pci_write_config8(dev1, 0x42, enables);
340 enables = pci_read_config8(dev1, 0x42);
341 printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
344 enables = pci_read_config8(dev1, 0x40);
345 printk_debug("enables in reg 0x40 0x%x\n", enables);
347 pci_write_config8(dev1, 0x40, enables);
348 enables = pci_read_config8(dev1, 0x40);
349 printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
351 // Enable prefetch buffers
352 enables = pci_read_config8(dev1, 0x41);
354 pci_write_config8(dev1, 0x41, enables);
356 // Lower thresholds (cause award does it)
357 enables = pci_read_config8(dev1, 0x43);
360 pci_write_config8(dev1, 0x43, enables);
362 // PIO read prefetch counter (cause award does it)
363 pci_write_config8(dev1, 0x44, 0x18);
365 // Use memory read multiple
366 pci_write_config8(dev1, 0x45, 0x1c);
369 // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
370 // kevinh@ispiri.com - the standard linux drivers seem ass slow when
371 // used in native mode - I've changed back to classic
372 enables = pci_read_config8(dev1, 0x9);
373 printk_debug("enables in reg 0x9 0x%x\n", enables);
374 // by the book, set the low-order nibble to 0xa.
375 if (conf->enable_native_ide) {
377 // cf/cg silicon needs an 'f' here.
383 pci_write_config8(dev1, 0x9, enables);
384 enables = pci_read_config8(dev1, 0x9);
385 printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
387 // standard bios sets master bit.
388 enables = pci_read_config8(dev1, 0x4);
389 printk_debug("command in reg 0x4 0x%x\n", enables);
392 // No need for stepping - kevinh@ispiri.com
395 pci_write_config8(dev1, 0x4, enables);
396 enables = pci_read_config8(dev1, 0x4);
397 printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
399 if (! conf->enable_native_ide) {
400 // Use compatability mode - per award bios
401 pci_write_config32(dev1, 0x10, 0x0);
402 pci_write_config32(dev1, 0x14, 0x0);
403 pci_write_config32(dev1, 0x18, 0x0);
404 pci_write_config32(dev1, 0x1c, 0x0);
406 // Force interrupts to use compat mode - just like Award bios
407 pci_write_config8(dev1, 0x3d, 00);
408 pci_write_config8(dev1, 0x3c, 0xff);
419 southbridge_init(struct chip *chip, enum chip_pass pass)
422 struct southbridge_via_vt8231_config *conf =
423 (struct southbridge_via_vt8231_config *)chip->chip_info;
426 case CONF_PASS_PRE_PCI:
427 vt8231_pci_enable(conf);
430 case CONF_PASS_POST_PCI:
432 printk_err("FUCK! ROUTING FIXUP!\n");
436 case CONF_PASS_PRE_BOOT:
437 printk_err("FUCK! ROUTING FIXUP!\n");
447 static void enumerate(struct chip *chip)
449 extern struct device_operations default_pci_ops_bus;
450 chip_enumerate(chip);
451 chip->dev->ops = &default_pci_ops_bus;
454 struct chip_control southbridge_via_vt8231_control = {
455 .enumerate = enumerate,
456 enable: southbridge_init,