3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
7 #include <device/chip.h>
8 #include <console/console.h>
12 void pc_keyboard_init(void);
16 printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
19 static void usb_on(int enable)
23 /* Base 8231 controller */
24 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
25 /* USB controller 1 */
26 device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
27 /* USB controller 2 */
28 device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
33 pci_write_config8(dev2, 0x3c, 0x05);
34 pci_write_config8(dev2, 0x04, 0x07);
36 pci_write_config8(dev2, 0x3c, 0x00);
37 pci_write_config8(dev2, 0x04, 0x00);
42 regval = pci_read_config8(dev0, 0x50);
47 pci_write_config8(dev0, 0x50, regval);
53 pci_write_config8(dev3, 0x3c, 0x05);
54 pci_write_config8(dev3, 0x04, 0x07);
56 pci_write_config8(dev3, 0x3c, 0x00);
57 pci_write_config8(dev3, 0x04, 0x00);
62 regval = pci_read_config8(dev0, 0x50);
67 pci_write_config8(dev0, 0x50, regval);
71 static void keyboard_on(void)
75 /* Base 8231 controller */
76 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
78 /* kevinh/Ispiri - update entire function to use
79 new pci_write_config8 */
82 regval = pci_read_config8(dev0, 0x51);
84 pci_write_config8(dev0, 0x51, regval);
86 init_pc_keyboard(0x60, 0x64, 0);
89 static void nvram_on(void)
92 * the VIA 8231 South has a very different nvram setup than the
94 * turn on ProMedia nvram.
95 * TO DO: use the PciWriteByte function here.
99 * kevinh/Ispiri - I don't think this is the correct address/value
100 * intel_conf_writeb(0x80008841, 0xFF);
106 * Enable the ethernet device and turn off stepping (because it is integrated
107 * inside the southbridge)
109 static void ethernet_fixup()
114 printk_info("Ethernet fixup\n");
116 edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
118 printk_debug("Configuring VIA LAN\n");
120 /* We don't need stepping - though the device supports it */
121 byte = pci_read_config8(edev, PCI_COMMAND);
122 byte &= ~PCI_COMMAND_WAIT;
123 pci_write_config8(edev, PCI_COMMAND, byte);
125 printk_debug("VIA LAN not found\n");
130 /* we need to do things in this function so that PCI scan will find
131 * them. One problem here is that we can't use ANY of the new device
132 * stuff. This work here precedes all that.
133 * Fundamental problem with linuxbios V2 architecture.
134 * You can't do pci control in the C code without having done a PCI scan.
135 * But in some cases you need to to pci control in the c code before doing
136 * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
137 * that has functions with the same name but different type signatures
138 * (e.g. device_t). This needs to get fixed. We need low-level pci scans
141 static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
144 unsigned long busdevfn = 0x8000;
145 if (conf->enable_ide) {
146 printk_debug("%s: enabling IDE function\n", __FUNCTION__);
153 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
156 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
157 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
158 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
161 Our IDSEL mappings are as follows
162 PCI slot is AD31 (device 15) (00:14.0)
163 Southbridge is AD28 (device 12) (00:11.0)
165 static void pci_routing_fixup(void)
169 dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
170 printk_info("%s: dev is %p\n", __FUNCTION__, dev);
172 /* initialize PCI interupts - these assignments depend
173 on the PCB routing of PINTA-D
180 pci_write_config8(dev, 0x55, 0xb0);
181 pci_write_config8(dev, 0x56, 0xa5);
182 pci_write_config8(dev, 0x57, 0xc0);
185 // Standard southbridge components
186 printk_info("setting southbridge\n");
187 pci_assign_irqs(0, 0x11, southbridgeIrqs);
189 // Ethernet built into southbridge
190 printk_info("setting ethernet\n");
191 pci_assign_irqs(0, 0x12, enetIrqs);
194 printk_info("setting pci slot\n");
195 pci_assign_irqs(0, 0x14, slotIrqs);
196 printk_info("%s: DONE\n", __FUNCTION__);
204 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
207 for(i = 0; i < 256; i += 16) {
208 printk_debug("0x%x: ", i);
209 for(j = 0; j < 16; j++) {
210 printk_debug("%02x ", pci_read_config8(dev0, i+j));
216 static void vt8231_init(struct southbridge_via_vt8231_config *conf)
218 unsigned char enables;
223 // to do: use the pcibios_find function here, instead of
224 // hard coding the devfn.
225 // done - kevinh/Ispiri
226 printk_debug("vt8231 init\n");
227 /* Base 8231 controller */
228 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
230 dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
231 /* Power management controller */
232 devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
234 // enable the internal I/O decode
235 enables = pci_read_config8(dev0, 0x6C);
237 pci_write_config8(dev0, 0x6C, enables);
239 // Map 4MB of FLASH into the address space
240 pci_write_config8(dev0, 0x41, 0x7f);
242 // Set bit 6 of 0x40, because Award does it (IO recovery time)
243 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
244 // interrupts can be properly marked as level triggered.
245 enables = pci_read_config8(dev0, 0x40);
246 pci_write_config8(dev0, 0x40, enables);
248 // Set 0x42 to 0xf0 to match Award bios
249 enables = pci_read_config8(dev0, 0x42);
251 pci_write_config8(dev0, 0x42, enables);
253 // Set bit 3 of 0x4a, to match award (dummy pci request)
254 enables = pci_read_config8(dev0, 0x4a);
256 pci_write_config8(dev0, 0x4a, enables);
258 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
259 enables = pci_read_config8(dev0, 0x4f);
261 pci_write_config8(dev0, 0x4f, enables);
263 // Set 0x58 to 0x03 to match Award
264 pci_write_config8(dev0, 0x58, 0x03);
266 // enable the ethernet/RTC
268 enables = pci_read_config8(dev0, 0x51);
270 pci_write_config8(dev0, 0x51, enables);
274 // enable com1 and com2.
275 if (conf->enable_com_ports) {
276 enables = pci_read_config8(dev0, 0x6e);
278 /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
279 * is enable com port a as com1 kevinh/Ispiri - Old code
280 * thought 0x01 would make it com1, that was wrong enables =
281 * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
282 * enables); // note: this is also a redo of some port of
283 * assembly, but we want everything up.
286 /* set com1 to 115 kbaud not clear how to do this yet.
287 * forget it; done in assembly.
291 // enable IDE, since Linux won't do it.
292 // First do some more things to devfn (17,0)
293 // note: this should already be cleared, according to the book.
294 enables = pci_read_config8(dev0, 0x50);
295 printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
296 enables &= ~8; // need manifest constant here!
297 printk_debug("set IDE reg. 50 to 0x%x\n", enables);
298 pci_write_config8(dev0, 0x50, enables);
300 // set default interrupt values (IDE)
301 enables = pci_read_config8(dev0, 0x4c);
302 printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
303 // clear out whatever was there.
306 printk_debug("setting reg. 4c to 0x%x\n", enables);
307 pci_write_config8(dev0, 0x4c, enables);
309 // set up the serial port interrupts.
310 // com2 to 3, com1 to 4
311 pci_write_config8(dev0, 0x46, 0x04);
312 pci_write_config8(dev0, 0x47, 0x03);
313 pci_write_config8(dev0, 0x6e, 0x98);
315 // Power management setup
317 // Set ACPI base address to IO 0x4000
318 pci_write_config32(devpwr, 0x48, 0x4001);
320 // Enable ACPI access (and setup like award)
321 pci_write_config8(devpwr, 0x41, 0x84);
323 // Set hardware monitor base address to IO 0x6000
324 pci_write_config32(devpwr, 0x70, 0x6001);
326 // Enable hardware monitor (and setup like award)
327 pci_write_config8(devpwr, 0x74, 0x01);
329 // set IO base address to 0x5000
330 pci_write_config32(devpwr, 0x90, 0x5001);
333 pci_write_config8(devpwr, 0xd2, 0x01);
338 if (! conf->enable_native_ide) {
339 // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
340 // interrupts. Using PCI ints confuses linux for some reason.
342 printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
343 enables = pci_read_config8(dev1, 0x42);
344 printk_debug("enables in reg 0x42 0x%x\n", enables);
345 enables &= ~0xc0; // compatability mode
346 pci_write_config8(dev1, 0x42, enables);
347 enables = pci_read_config8(dev1, 0x42);
348 printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
351 enables = pci_read_config8(dev1, 0x40);
352 printk_debug("enables in reg 0x40 0x%x\n", enables);
354 pci_write_config8(dev1, 0x40, enables);
355 enables = pci_read_config8(dev1, 0x40);
356 printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
358 // Enable prefetch buffers
359 enables = pci_read_config8(dev1, 0x41);
361 pci_write_config8(dev1, 0x41, enables);
363 // Lower thresholds (cause award does it)
364 enables = pci_read_config8(dev1, 0x43);
367 pci_write_config8(dev1, 0x43, enables);
369 // PIO read prefetch counter (cause award does it)
370 pci_write_config8(dev1, 0x44, 0x18);
372 // Use memory read multiple
373 pci_write_config8(dev1, 0x45, 0x1c);
376 // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
377 // kevinh@ispiri.com - the standard linux drivers seem ass slow when
378 // used in native mode - I've changed back to classic
379 enables = pci_read_config8(dev1, 0x9);
380 printk_debug("enables in reg 0x9 0x%x\n", enables);
381 // by the book, set the low-order nibble to 0xa.
382 if (conf->enable_native_ide) {
384 // cf/cg silicon needs an 'f' here.
390 pci_write_config8(dev1, 0x9, enables);
391 enables = pci_read_config8(dev1, 0x9);
392 printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
394 // standard bios sets master bit.
395 enables = pci_read_config8(dev1, 0x4);
396 printk_debug("command in reg 0x4 0x%x\n", enables);
399 // No need for stepping - kevinh@ispiri.com
402 pci_write_config8(dev1, 0x4, enables);
403 enables = pci_read_config8(dev1, 0x4);
404 printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
406 if (! conf->enable_native_ide) {
407 // Use compatability mode - per award bios
408 pci_write_config32(dev1, 0x10, 0x0);
409 pci_write_config32(dev1, 0x14, 0x0);
410 pci_write_config32(dev1, 0x18, 0x0);
411 pci_write_config32(dev1, 0x1c, 0x0);
413 // Force interrupts to use compat mode - just like Award bios
414 pci_write_config8(dev1, 0x3d, 00);
415 pci_write_config8(dev1, 0x3c, 0xff);
419 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
420 pci_write_config8(dev0, 0x40, 0x54);
427 static void southbridge_init(struct chip *chip, enum chip_pass pass)
430 struct southbridge_via_vt8231_config *conf =
431 (struct southbridge_via_vt8231_config *)chip->chip_info;
434 case CONF_PASS_PRE_PCI:
435 vt8231_pci_enable(conf);
438 case CONF_PASS_POST_PCI:
443 case CONF_PASS_PRE_BOOT:
453 static void enumerate(struct chip *chip)
455 extern struct device_operations default_pci_ops_bus;
456 chip_enumerate(chip);
457 chip->dev->ops = &default_pci_ops_bus;
460 struct chip_control southbridge_via_vt8231_control = {
461 .enumerate = enumerate,
462 .enable = southbridge_init,