3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
7 #include <console/console.h>
11 void pc_keyboard_init(void);
15 printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
18 static void usb_on(int enable)
22 /* Base 8231 controller */
23 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
24 /* USB controller 1 */
25 device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
26 /* USB controller 2 */
27 device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
32 pci_write_config8(dev2, 0x3c, 0x05);
33 pci_write_config8(dev2, 0x04, 0x07);
35 pci_write_config8(dev2, 0x3c, 0x00);
36 pci_write_config8(dev2, 0x04, 0x00);
41 regval = pci_read_config8(dev0, 0x50);
46 pci_write_config8(dev0, 0x50, regval);
52 pci_write_config8(dev3, 0x3c, 0x05);
53 pci_write_config8(dev3, 0x04, 0x07);
55 pci_write_config8(dev3, 0x3c, 0x00);
56 pci_write_config8(dev3, 0x04, 0x00);
61 regval = pci_read_config8(dev0, 0x50);
66 pci_write_config8(dev0, 0x50, regval);
70 static void keyboard_on(void)
74 /* Base 8231 controller */
75 device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
77 /* kevinh/Ispiri - update entire function to use
78 new pci_write_config8 */
81 regval = pci_read_config8(dev0, 0x51);
83 pci_write_config8(dev0, 0x51, regval);
85 init_pc_keyboard(0x60, 0x64, 0);
88 static void nvram_on(void)
91 * the VIA 8231 South has a very different nvram setup than the
93 * turn on ProMedia nvram.
94 * TO DO: use the PciWriteByte function here.
98 * kevinh/Ispiri - I don't think this is the correct address/value
99 * intel_conf_writeb(0x80008841, 0xFF);
105 * Enable the ethernet device and turn off stepping (because it is integrated
106 * inside the southbridge)
108 static void ethernet_fixup()
113 printk_info("Ethernet fixup\n");
115 edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
117 printk_debug("Configuring VIA LAN\n");
119 /* We don't need stepping - though the device supports it */
120 byte = pci_read_config8(edev, PCI_COMMAND);
121 byte &= ~PCI_COMMAND_WAIT;
122 pci_write_config8(edev, PCI_COMMAND, byte);
124 printk_debug("VIA LAN not found\n");
129 /* we need to do things in this function so that PCI scan will find
130 * them. One problem here is that we can't use ANY of the new device
131 * stuff. This work here precedes all that.
132 * Fundamental problem with linuxbios V2 architecture.
133 * You can't do pci control in the C code without having done a PCI scan.
134 * But in some cases you need to to pci control in the c code before doing
135 * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
136 * that has functions with the same name but different type signatures
137 * (e.g. device_t). This needs to get fixed. We need low-level pci scans
140 static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
143 unsigned long busdevfn = 0x8000;
144 if (conf->enable_ide) {
145 printk_debug("%s: enabling IDE function\n", __FUNCTION__);
152 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
155 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
156 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
157 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
160 Our IDSEL mappings are as follows
161 PCI slot is AD31 (device 15) (00:14.0)
162 Southbridge is AD28 (device 12) (00:11.0)
164 static void pci_routing_fixup(struct device *dev)
167 printk_info("%s: dev is %p\n", __FUNCTION__, dev);
169 /* initialize PCI interupts - these assignments depend
170 on the PCB routing of PINTA-D
177 pci_write_config8(dev, 0x55, 0xb0);
178 pci_write_config8(dev, 0x56, 0xa5);
179 pci_write_config8(dev, 0x57, 0xc0);
182 // Standard southbridge components
183 printk_info("setting southbridge\n");
184 pci_assign_irqs(0, 0x11, southbridgeIrqs);
186 // Ethernet built into southbridge
187 printk_info("setting ethernet\n");
188 pci_assign_irqs(0, 0x12, enetIrqs);
191 printk_info("setting pci slot\n");
192 pci_assign_irqs(0, 0x14, slotIrqs);
193 printk_info("%s: DONE\n", __FUNCTION__);
201 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
204 for(i = 0; i < 256; i += 16) {
205 printk_debug("0x%x: ", i);
206 for(j = 0; j < 16; j++) {
207 printk_debug("%02x ", pci_read_config8(dev0, i+j));
213 static void vt8231_init(struct southbridge_via_vt8231_config *conf)
215 unsigned char enables;
220 // to do: use the pcibios_find function here, instead of
221 // hard coding the devfn.
222 // done - kevinh/Ispiri
223 printk_debug("vt8231 init\n");
224 /* Base 8231 controller */
225 dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
227 dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
228 /* Power management controller */
229 devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
231 // enable the internal I/O decode
232 enables = pci_read_config8(dev0, 0x6C);
234 pci_write_config8(dev0, 0x6C, enables);
236 // Map 4MB of FLASH into the address space
237 pci_write_config8(dev0, 0x41, 0x7f);
239 // Set bit 6 of 0x40, because Award does it (IO recovery time)
240 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
241 // interrupts can be properly marked as level triggered.
242 enables = pci_read_config8(dev0, 0x40);
243 pci_write_config8(dev0, 0x40, enables);
245 // Set 0x42 to 0xf0 to match Award bios
246 enables = pci_read_config8(dev0, 0x42);
248 pci_write_config8(dev0, 0x42, enables);
250 // Set bit 3 of 0x4a, to match award (dummy pci request)
251 enables = pci_read_config8(dev0, 0x4a);
253 pci_write_config8(dev0, 0x4a, enables);
255 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
256 enables = pci_read_config8(dev0, 0x4f);
258 pci_write_config8(dev0, 0x4f, enables);
260 // Set 0x58 to 0x03 to match Award
261 pci_write_config8(dev0, 0x58, 0x03);
263 // enable the ethernet/RTC
265 enables = pci_read_config8(dev0, 0x51);
267 pci_write_config8(dev0, 0x51, enables);
271 // enable com1 and com2.
272 if (conf->enable_com_ports) {
273 enables = pci_read_config8(dev0, 0x6e);
275 /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
276 * is enable com port a as com1 kevinh/Ispiri - Old code
277 * thought 0x01 would make it com1, that was wrong enables =
278 * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
279 * enables); // note: this is also a redo of some port of
280 * assembly, but we want everything up.
283 /* set com1 to 115 kbaud not clear how to do this yet.
284 * forget it; done in assembly.
288 // enable IDE, since Linux won't do it.
289 // First do some more things to devfn (17,0)
290 // note: this should already be cleared, according to the book.
291 enables = pci_read_config8(dev0, 0x50);
292 printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
293 enables &= ~8; // need manifest constant here!
294 printk_debug("set IDE reg. 50 to 0x%x\n", enables);
295 pci_write_config8(dev0, 0x50, enables);
297 // set default interrupt values (IDE)
298 enables = pci_read_config8(dev0, 0x4c);
299 printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
300 // clear out whatever was there.
303 printk_debug("setting reg. 4c to 0x%x\n", enables);
304 pci_write_config8(dev0, 0x4c, enables);
306 // set up the serial port interrupts.
307 // com2 to 3, com1 to 4
308 pci_write_config8(dev0, 0x46, 0x04);
309 pci_write_config8(dev0, 0x47, 0x03);
310 pci_write_config8(dev0, 0x6e, 0x98);
312 // Power management setup
314 // Set ACPI base address to IO 0x4000
315 pci_write_config32(devpwr, 0x48, 0x4001);
317 // Enable ACPI access (and setup like award)
318 pci_write_config8(devpwr, 0x41, 0x84);
320 // Set hardware monitor base address to IO 0x6000
321 pci_write_config32(devpwr, 0x70, 0x6001);
323 // Enable hardware monitor (and setup like award)
324 pci_write_config8(devpwr, 0x74, 0x01);
326 // set IO base address to 0x5000
327 pci_write_config32(devpwr, 0x90, 0x5001);
330 pci_write_config8(devpwr, 0xd2, 0x01);
335 if (! conf->enable_native_ide) {
336 // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
337 // interrupts. Using PCI ints confuses linux for some reason.
339 printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
340 enables = pci_read_config8(dev1, 0x42);
341 printk_debug("enables in reg 0x42 0x%x\n", enables);
342 enables &= ~0xc0; // compatability mode
343 pci_write_config8(dev1, 0x42, enables);
344 enables = pci_read_config8(dev1, 0x42);
345 printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
348 enables = pci_read_config8(dev1, 0x40);
349 printk_debug("enables in reg 0x40 0x%x\n", enables);
351 pci_write_config8(dev1, 0x40, enables);
352 enables = pci_read_config8(dev1, 0x40);
353 printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
355 // Enable prefetch buffers
356 enables = pci_read_config8(dev1, 0x41);
358 pci_write_config8(dev1, 0x41, enables);
360 // Lower thresholds (cause award does it)
361 enables = pci_read_config8(dev1, 0x43);
364 pci_write_config8(dev1, 0x43, enables);
366 // PIO read prefetch counter (cause award does it)
367 pci_write_config8(dev1, 0x44, 0x18);
369 // Use memory read multiple
370 pci_write_config8(dev1, 0x45, 0x1c);
373 // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
374 // kevinh@ispiri.com - the standard linux drivers seem ass slow when
375 // used in native mode - I've changed back to classic
376 enables = pci_read_config8(dev1, 0x9);
377 printk_debug("enables in reg 0x9 0x%x\n", enables);
378 // by the book, set the low-order nibble to 0xa.
379 if (conf->enable_native_ide) {
381 // cf/cg silicon needs an 'f' here.
387 pci_write_config8(dev1, 0x9, enables);
388 enables = pci_read_config8(dev1, 0x9);
389 printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
391 // standard bios sets master bit.
392 enables = pci_read_config8(dev1, 0x4);
393 printk_debug("command in reg 0x4 0x%x\n", enables);
396 // No need for stepping - kevinh@ispiri.com
399 pci_write_config8(dev1, 0x4, enables);
400 enables = pci_read_config8(dev1, 0x4);
401 printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
403 if (! conf->enable_native_ide) {
404 // Use compatability mode - per award bios
405 pci_write_config32(dev1, 0x10, 0x0);
406 pci_write_config32(dev1, 0x14, 0x0);
407 pci_write_config32(dev1, 0x18, 0x0);
408 pci_write_config32(dev1, 0x1c, 0x0);
410 // Force interrupts to use compat mode - just like Award bios
411 pci_write_config8(dev1, 0x3d, 00);
412 pci_write_config8(dev1, 0x3c, 0xff);
416 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
417 pci_write_config8(dev0, 0x40, 0x54);
424 static void southbridge_init(struct device *dev) {
425 vt8231_init(dev->chip_info);
426 pci_routing_fixup(dev);
429 struct device_operations vt8231_dev_ops = {
430 .init = &southbridge_init,
433 static void southbridge_enable(struct device *dev)
435 dev->ops = &vt8231_dev_ops;
438 struct chip_operations southbridge_via_vt8231_ops = {
439 .enable_dev = southbridge_enable,