src/southbridge/via/k8t890/k8t890_traf_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <console/console.h>
  24 #include "k8t890.h"
  25
  26 extern unsigned long log2(unsigned long x);
  27
  28 static void mmconfig_set_resources(device_t dev)
  29 {
  30         struct resource *resource;
  31         u8 reg;
  32
  33         resource = find_resource(dev, K8T890_MMCONFIG_MBAR);
  34         if (resource) {
  35                 report_resource_stored(dev, resource, "<mmconfig>");
  36
  37                 /* Remember this resource has been stored. */
  38                 resource->flags |= IORESOURCE_STORED;
  39                 pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
  40                                   (resource->base >> 28));
  41                 reg = pci_read_config8(dev, 0x60);
  42                 reg |= 0x3;
  43                 /* Enable MMCONFIG decoding. */
  44                 pci_write_config8(dev, 0x60, reg);
  45         }
  46         pci_dev_set_resources(dev);
  47 }
  48
  49 static void apic_mmconfig_read_resources(device_t dev)
  50 {
  51         struct resource *res;
  52         pci_dev_read_resources(dev);
  53
  54         res = new_resource(dev, 0x40);
  55         /* NB APIC fixed to this address. */
  56         res->base = K8T890_APIC_BASE;
  57         res->size = 256;
  58         res->limit = res->base + res->size - 1;
  59         res->align = 8;
  60         res->gran = 8;
  61         res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
  62                      IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  63
  64         /* Add an MMCONFIG resource. */
  65         res = new_resource(dev, K8T890_MMCONFIG_MBAR);
  66         res->size = 256 * 1024 * 1024;
  67         res->align = log2(res->size);
  68         res->gran = log2(res->size);
  69         res->limit = 0xffffffff;        /* 4G */
  70         res->flags = IORESOURCE_MEM;
  71 }
  72
  73 static void traf_ctrl_enable_generic(struct device *dev)
  74 {
  75         volatile u32 *apic;
  76         u32 data;
  77
  78         /* no device2 redirect, enable just one device behind
  79          * bridge device 2 and device 3).
  80          */
  81         pci_write_config8(dev, 0x60, 0x08);
  82
  83         /* Will enable MMCONFIG later. */
  84         pci_write_config8(dev, 0x64, 0x23);
  85         /* No extended RCRB Base Address. */
  86         pci_write_config8(dev, 0x62, 0x00);
  87
  88         /* Offset80 ->95 bit 4 in 1 in Award. */
  89
  90         /* Enable APIC, to K8T890_APIC_BASE. */
  91         pci_write_config8(dev, 0x41, 0x00);
  92         pci_write_config8(dev, 0x40, 0x8c);
  93         /* BT_INTR enable, APIC Nonshare Mode Enable. */
  94         pci_write_config8(dev, 0x42, 0x5);
  95
  96         apic = (u32 *)K8T890_APIC_BASE;
  97
  98         /* Set APIC to FSB transported messages. */
  99         apic[0] = 3;
 100         data = apic[4];
 101         apic[4] = (data & 0xFFFFFE) | 1;
 102
 103         /* Set APIC ID. */
 104         apic[0] = 0;
 105         data = apic[4];
 106         apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
 107 }
 108
 109 static void traf_ctrl_enable_k8m890(struct device *dev)
 110 {
 111         traf_ctrl_enable_generic(dev);
 112 }
 113
 114 static void traf_ctrl_enable_k8t890(struct device *dev)
 115 {
 116         u8 reg;
 117
 118         traf_ctrl_enable_generic(dev);
 119
 120         /* Enable D3F1-D3F3 */
 121         reg = pci_read_config8(dev, 0x60);
 122         pci_write_config8(dev, 0x60, 0x80 | reg);
 123 }
 124
 125 static const struct device_operations traf_ctrl_ops_m = {
 126         .read_resources         = apic_mmconfig_read_resources,
 127         .set_resources          = mmconfig_set_resources,
 128         .enable_resources       = pci_dev_enable_resources,
 129         .enable                 = traf_ctrl_enable_k8m890,
 130         .ops_pci                = 0,
 131 };
 132
 133 static const struct device_operations traf_ctrl_ops_t = {
 134         .read_resources         = apic_mmconfig_read_resources,
 135         .set_resources          = mmconfig_set_resources,
 136         .enable_resources       = pci_dev_enable_resources,
 137         .enable                 = traf_ctrl_enable_k8t890,
 138         .ops_pci                = 0,
 139 };
 140
 141 static const struct pci_driver northbridge_driver_t __pci_driver = {
 142         .ops    = &traf_ctrl_ops_t,
 143         .vendor = PCI_VENDOR_ID_VIA,
 144         .device = PCI_DEVICE_ID_VIA_K8T890CE_5,
 145 };
 146
 147 static const struct pci_driver northbridge_driver_m __pci_driver = {
 148         .ops    = &traf_ctrl_ops_m,
 149         .vendor = PCI_VENDOR_ID_VIA,
 150         .device = PCI_DEVICE_ID_VIA_K8M890CE_5,
 151 };