2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pciexp.h>
24 #include <device/pci_ids.h>
27 static void peg_init(struct device *dev)
31 printk_debug("Configuring PCIe PEG\n");
35 reg = pci_read_config8(dev, 0x50);
36 pci_write_config8(dev, 0x50, reg | 0x10);
38 /* Award has 0xb, VIA recomends 0x4. */
39 pci_write_config8(dev, 0xe1, 0xb);
42 * pci_write_config8(dev, 0xe2, 0x0);
43 * pci_write_config8(dev, 0xe3, 0x92);
46 /* Set replay timer limit. */
47 pci_write_config8(dev, 0xb1, 0xf0);
49 /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */
50 reg = pci_read_config8(dev, 0xb8);
51 pci_write_config8(dev, 0xb8, reg | 0x1);
54 * Downstream wait and Upstream Checking Malformed TLP through
55 * "Byte Enable Rule" And "Over 4K Boundary Rule".
57 reg = pci_read_config8(dev, 0xa4);
58 pci_write_config8(dev, 0xa4, reg | 0x30);
61 reg = pci_read_config8(dev, 0x50);
62 pci_write_config8(dev, 0x50, reg & ~0x10);
67 static void pcie_init(struct device *dev)
71 printk_debug("Configuring PCIe PEXs\n");
75 reg = pci_read_config8(dev, 0x50);
76 pci_write_config8(dev, 0x50, reg | 0x10);
78 /* Award has 0xb, VIA recommends 0x4. */
79 pci_write_config8(dev, 0xe1, 0xb);
80 /* Set replay timer limit. */
81 pci_write_config8(dev, 0xb1, 0xf0);
84 reg = pci_read_config8(dev, 0x50);
85 pci_write_config8(dev, 0x50, reg & ~0x10);
90 static const struct device_operations peg_ops = {
91 .read_resources = pci_bus_read_resources,
92 .set_resources = pci_dev_set_resources,
93 .enable_resources = pci_bus_enable_resources,
95 .scan_bus = pciexp_scan_bridge,
96 .reset_bus = pci_bus_reset,
100 static const struct device_operations pcie_ops = {
101 .read_resources = pci_bus_read_resources,
102 .set_resources = pci_dev_set_resources,
103 .enable_resources = pci_bus_enable_resources,
105 .scan_bus = pciexp_scan_bridge,
106 .reset_bus = pci_bus_reset,
110 static const struct pci_driver northbridge_driver __pci_driver = {
112 .vendor = PCI_VENDOR_ID_VIA,
113 .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG,
116 static const struct pci_driver pcie_drvd3f0 __pci_driver = {
118 .vendor = PCI_VENDOR_ID_VIA,
119 .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0,
122 static const struct pci_driver pcie_drvd3f1 __pci_driver = {
124 .vendor = PCI_VENDOR_ID_VIA,
125 .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1,
128 static const struct pci_driver pcie_drvd3f2 __pci_driver = {
130 .vendor = PCI_VENDOR_ID_VIA,
131 .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2,
134 static const struct pci_driver pcie_drvd3f3 __pci_driver = {
136 .vendor = PCI_VENDOR_ID_VIA,
137 .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3,