src/southbridge/via/k8t890/k8t890_host_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License v2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25
  26 /* this may be later merged */
  27
  28 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  29 static void host_ctrl_enable_k8t890(struct device *dev)
  30 {
  31         dump_south(dev);
  32
  33         /*
  34          * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
  35          * requests to 3.
  36          */
  37         pci_write_config8(dev, 0xa0, 0x13);
  38
  39         /* Disable NVRAM and enable non-posted PCI writes. */
  40         pci_write_config8(dev, 0xa1, 0x8e);
  41
  42         /*
  43          * NVRAM I/O base 0xe00-0xeff, but it is disabled.
  44          * Some bits are set and reserved.
  45          */
  46         pci_write_config8(dev, 0xa2, 0x0e);
  47         /* Arbitration control, some bits are reserved. */
  48         pci_write_config8(dev, 0xa5, 0x3c);
  49
  50         /* Arbitration control 2 */
  51         pci_write_config8(dev, 0xa6, 0x80);
  52
  53         /* this will be possibly removed, when I figure out
  54          * if the ROM SIP is good, second reason is that the
  55          * unknown bits are AGP related, which are dummy on K8T890
  56          */
  57
  58         writeback(dev, 0xa0, 0x13);     /* Bit4 is reserved! */
  59         writeback(dev, 0xa1, 0x8e);     /* Some bits are reserved. */
  60         writeback(dev, 0xa2, 0x0e);     /* I/O NVRAM base 0xe00-0xeff disabled. */
  61         writeback(dev, 0xa3, 0x31);
  62         writeback(dev, 0xa4, 0x30);
  63
  64         writeback(dev, 0xa5, 0x3c);     /* Some bits reserved. */
  65         writeback(dev, 0xa6, 0x80);     /* Some bits reserved. */
  66         writeback(dev, 0xa7, 0x86);     /* Some bits reserved. */
  67         writeback(dev, 0xa8, 0x7f);     /* Some bits reserved. */
  68         writeback(dev, 0xa9, 0xcf);     /* Some bits reserved. */
  69         writeback(dev, 0xaa, 0x44);
  70         writeback(dev, 0xab, 0x22);
  71         writeback(dev, 0xac, 0x35);     /* Maybe bit0 is read-only? */
  72
  73         writeback(dev, 0xae, 0x22);
  74         writeback(dev, 0xaf, 0x40);
  75         /* b0 is missing. */
  76         writeback(dev, 0xb1, 0x13);
  77         writeback(dev, 0xb4, 0x02);     /* Some bits are reserved. */
  78         writeback(dev, 0xc0, 0x20);
  79         writeback(dev, 0xc1, 0xaa);
  80         writeback(dev, 0xc2, 0xaa);
  81         writeback(dev, 0xc3, 0x02);
  82         writeback(dev, 0xc4, 0x50);
  83         writeback(dev, 0xc5, 0x50);
  84
  85         dump_south(dev);
  86 }
  87
  88 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  89 static void host_ctrl_enable_k8m890(struct device *dev) {
  90
  91         /*
  92          * Set PCI to HT outstanding requests to 03.
  93          * Bit 4 32 AGP ADS Read Outstanding Request Number
  94          */
  95         pci_write_config8(dev, 0xa0, 0x13);
  96
  97         /* Disable NVRAM and enable non-posted PCI writes. */
  98         pci_write_config8(dev, 0xa1, 0x8e);
  99
 100         /*
 101          * NVRAM I/O base 0xe00-0xeff, but it is disabled.
 102          */
 103
 104         pci_write_config8(dev, 0xa2, 0x0e);
 105         /* Arbitration control  */
 106         pci_write_config8(dev, 0xa5, 0x3c);
 107
 108         /* Arbitration control 2 */
 109         pci_write_config8(dev, 0xa6, 0x82);
 110
 111 }
 112
 113 static const struct device_operations host_ctrl_ops_t = {
 114         .read_resources         = pci_dev_read_resources,
 115         .set_resources          = pci_dev_set_resources,
 116         .enable_resources       = pci_dev_enable_resources,
 117         .enable                 = host_ctrl_enable_k8t890,
 118         .ops_pci                = 0,
 119 };
 120
 121 static const struct device_operations host_ctrl_ops_m = {
 122         .read_resources         = pci_dev_read_resources,
 123         .set_resources          = pci_dev_set_resources,
 124         .enable_resources       = pci_dev_enable_resources,
 125         .enable                 = host_ctrl_enable_k8m890,
 126         .ops_pci                = 0,
 127 };
 128
 129 static const struct pci_driver northbridge_driver_t __pci_driver = {
 130         .ops    = &host_ctrl_ops_t,
 131         .vendor = PCI_VENDOR_ID_VIA,
 132         .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
 133 };
 134
 135 static const struct pci_driver northbridge_driver_m __pci_driver = {
 136         .ops    = &host_ctrl_ops_m,
 137         .vendor = PCI_VENDOR_ID_VIA,
 138         .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
 139 };