2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License v2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * Seems the link and width of HT link needs to be setup too, you need to
22 * generate PCI reset or LDTSTOP to apply.
27 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
28 static ldtreg[3] = {0x86, 0xa6, 0xc6};
30 /* This functions sets KT890 link frequency and width to same values as
31 * it has been setup on K8 side, by AMD NB init.
34 u8 k8t890_early_setup_ht(void)
36 u8 awidth, afreq, cldtfreq;
37 u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
40 /* check if connected non coherent, initcomplete (find the SB on K8 side) */
41 if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
43 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
45 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) {
49 print_debug("K8T890 found at LDT ");
50 print_debug_hex8(ldtnr);
52 /* get the maximum widths for both sides */
53 cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
54 cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7;
55 vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7;
56 vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7;
58 width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
59 print_debug(" Agreed on width: ");
60 print_debug_hex8(width);
62 awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
64 /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */
65 width = (width == 0x01) ? 0x11 : 0x00;
67 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width);
69 /* Get programmed HT freq at base 0x89 */
70 cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
71 print_debug(" CPU programmed to HT freq: ");
72 print_debug_hex8(cldtfreq);
74 print_debug(" VIA HT caps: ");
75 vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e);
76 print_debug_hex16(vldtcaps);
78 if (!(vldtcaps & (1 << cldtfreq ))) {
79 die("Chipset does not support desired HT frequency\n");
82 afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
83 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq);
87 if ((width == awidth) && (afreq == cldtfreq)) {