2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * Seems the link and width of HT link needs to be setup too, you need to
22 * generate PCI reset or LDTSTOP to apply.
30 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
31 #define K8T890_NVRAM_IO_BASE 0xf00
32 #define K8T890_MULTIPLE_FN_EN 0x4f
34 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
35 static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
37 /* This functions sets KT890 link frequency and width to same values as
38 * it has been setup on K8 side, by AMD NB init.
41 u8 k8t890_early_setup_ht(void)
43 u8 awidth, afreq, cldtfreq, reg;
44 u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
47 /* hack, enable NVRAM in chipset */
48 pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
51 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
54 pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
55 reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
57 pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
59 /* check if connected non coherent, initcomplete (find the SB on K8 side) */
61 if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
63 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
65 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) {
69 print_debug("K8T890 found at LDT ");
70 print_debug_hex8(ldtnr);
72 /* get the maximum widths for both sides */
73 cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
74 cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7;
75 vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7;
76 vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7;
78 width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
79 print_debug(" Agreed on width: ");
80 print_debug_hex8(width);
82 awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
84 /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */
85 width = (width == 0x01) ? 0x11 : 0x00;
87 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width);
89 /* Get programmed HT freq at base 0x89 */
90 cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
91 print_debug(" CPU programmed to HT freq: ");
92 print_debug_hex8(cldtfreq);
94 print_debug(" VIA HT caps: ");
95 vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e);
96 print_debug_hex16(vldtcaps);
98 if (!(vldtcaps & (1 << cldtfreq ))) {
99 die("Chipset does not support desired HT frequency\n");
102 afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
103 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq);
106 /* no reset needed */
107 if ((width == awidth) && (afreq == cldtfreq)) {
114 static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
117 printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
120 outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
124 outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
128 outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
135 static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
140 *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
144 *old_dword &= ~0xffff;
145 *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
149 *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
153 printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
157 /* this should be a function
158 struct cbmem_entry *get_cbmem_toc(void) {
161 #define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC))