2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ops.h>
23 #include <device/pci_ids.h>
24 #include <console/console.h>
26 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
27 * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
30 static void vt8237r_cfg(struct device *dev, struct device *devsb)
36 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
37 PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
40 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
41 PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
43 pci_write_config8(dev, 0x70, 0xc2);
46 pci_write_config8(dev, 0x72, 0xee);
47 pci_write_config8(dev, 0x73, 0x01);
48 pci_write_config8(dev, 0x74, 0x24);
49 pci_write_config8(dev, 0x75, 0x0f);
50 pci_write_config8(dev, 0x76, 0x50);
51 pci_write_config8(dev, 0x77, 0x08);
52 pci_write_config8(dev, 0x78, 0x01);
54 pci_write_config8(dev, 0x7c, 0x7f);
55 pci_write_config8(dev, 0x7f, 0x02);
57 /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
59 regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
60 pci_write_config8(dev, 0x57, regm);
62 regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
63 pci_write_config8(dev, 0x61, regm);
65 regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
66 pci_write_config8(dev, 0x62, regm);
68 regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
69 pci_write_config8(dev, 0xe6, regm);
71 regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
74 * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
75 * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
76 * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
83 /* Shadow page F + memhole copy */
84 regm = pci_read_config8(devfun3, 0x83);
85 pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
91 * Setup the V-Link for VT8237R, 8X mode.
93 * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
95 * REG DEF AW VIA-8X VIA-4X
96 * -----------------------------
97 * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88
98 * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88
99 * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01
100 * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11
101 * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98
102 * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77
103 * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11
104 * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01
105 * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
106 * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
109 static void vt8237r_vlink_init(struct device *dev)
114 * This init code is valid only for the VT8237R! For different
115 * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
116 * and VT8251) a different init code is required.
119 pci_write_config8(dev, 0xb5, 0x88);
120 pci_write_config8(dev, 0xb6, 0x88);
121 pci_write_config8(dev, 0xb7, 0x61);
123 reg = pci_read_config8(dev, 0xb4);
125 pci_write_config8(dev, 0xb4, reg);
127 pci_write_config8(dev, 0xb9, 0x98);
128 pci_write_config8(dev, 0xba, 0x77);
129 pci_write_config8(dev, 0xbb, 0x11);
131 reg = pci_read_config8(dev, 0xb8);
133 pci_write_config8(dev, 0xb8, reg);
135 pci_write_config8(dev, 0xb0, 0x06);
136 pci_write_config8(dev, 0xb1, 0x01);
138 /* Program V-link 8X 16bit full duplex, parity enabled. */
139 pci_write_config8(dev, 0x48, 0xa3);
142 static void ctrl_init(struct device *dev) {
144 /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
147 /* C2P Read ACK Return Priority */
148 /* PCI CFG Address bits[27:24] are used as extended register address
151 pci_write_config8(dev, 0x47, 0x30);
153 /* VT8237R specific configuration other SB are done in their own directories */
155 device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
156 PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
158 vt8237r_vlink_init(dev);
159 vt8237r_cfg(dev, devsb);
164 static const struct device_operations ctrl_ops = {
165 .read_resources = pci_dev_read_resources,
166 .set_resources = pci_dev_set_resources,
167 .enable_resources = pci_dev_enable_resources,
172 static const struct pci_driver northbridge_driver_t __pci_driver = {
174 .vendor = PCI_VENDOR_ID_VIA,
175 .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
178 static const struct pci_driver northbridge_driver_m __pci_driver = {
180 .vendor = PCI_VENDOR_ID_VIA,
181 .device = PCI_DEVICE_ID_VIA_K8M890CE_7,