src/southbridge/via/k8t890/k8t890_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License v2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25
  26 /**
  27  * Setup the V-Link for VT8237R, 8X mode.
  28  *
  29  * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
  30  *
  31  *                                               REG   DEF   AW  VIA-8X VIA-4X
  32  *                                               -----------------------------
  33  * NB V-Link Manual Driving Control strobe       0xb5  0x46  0x46  0x88  0x88
  34  * NB V-Link Manual Driving Control - Data       0xb6  0x46  0x46  0x88  0x88
  35  * NB V-Link Receiving Strobe Delay              0xb7  0x02  0x02  0x61  0x01
  36  * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
  37  * SB V-Link Strobe Drive Control                0xb9  0x00  0xa5  0x98  0x98
  38  * SB V-Link Data drive Control????              0xba  0x00  0xbb  0x77  0x77
  39  * SB V-Link Receive Strobe Delay????            0xbb  0x04  0x11  0x11  0x11
  40  * SB V-Link Compensation Control bit0 (use b9)  0xb8  0x00  0x01  0x01  0x01
  41  * V-Link CKG Control                            0xb0  0x05  0x05  0x06  0x03
  42  * V-Link CKG Control                            0xb1  0x05  0x05  0x01  0x03
  43  */
  44 static void ctrl_init_vt8237r(struct device *dev)
  45 {
  46         u8 reg;
  47
  48         /*
  49          * This init code is valid only for the VT8237R! For different
  50          * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
  51          * and VT8251) a different init code is required.
  52          */
  53         device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
  54                                          PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
  55         if (!devsb)
  56                 return;
  57
  58         pci_write_config8(dev, 0xb5, 0x88);
  59         pci_write_config8(dev, 0xb6, 0x88);
  60         pci_write_config8(dev, 0xb7, 0x61);
  61
  62         reg = pci_read_config8(dev, 0xb4);
  63         reg |= 0x11;
  64         pci_write_config8(dev, 0xb4, reg);
  65
  66         pci_write_config8(dev, 0xb9, 0x98);
  67         pci_write_config8(dev, 0xba, 0x77);
  68         pci_write_config8(dev, 0xbb, 0x11);
  69
  70         reg = pci_read_config8(dev, 0xb8);
  71         reg |= 0x1;
  72         pci_write_config8(dev, 0xb8, reg);
  73
  74         pci_write_config8(dev, 0xb0, 0x06);
  75         pci_write_config8(dev, 0xb1, 0x01);
  76
  77         /* Program V-link 8X 16bit full duplex, parity enabled. */
  78         pci_write_config8(dev, 0x48, 0xa3);
  79 }
  80
  81 static void ctrl_enable(struct device *dev)
  82 {
  83         u8 regm, regm2, regm3;
  84         device_t devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  85                                            PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
  86
  87         /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
  88            should to 1 */
  89
  90         /* C2P Read ACK Return Priority */
  91         /* PCI CFG Address bits[27:24] are used as extended register address
  92            bit[11:8] */
  93         pci_write_config8(dev, 0x47, 0x30);
  94         /* Magic init. This is not well documented :/ */
  95         pci_write_config8(dev, 0x70, 0xc2);
  96
  97         /* PCI Control */
  98         pci_write_config8(dev, 0x72, 0xee);
  99         pci_write_config8(dev, 0x73, 0x01);
 100         pci_write_config8(dev, 0x74, 0x24);
 101         pci_write_config8(dev, 0x75, 0x0f);
 102         pci_write_config8(dev, 0x76, 0x50);
 103         pci_write_config8(dev, 0x77, 0x08);
 104         pci_write_config8(dev, 0x78, 0x01);
 105         /* APIC on HT */
 106         pci_write_config8(dev, 0x7c, 0x7f);
 107         pci_write_config8(dev, 0x7f, 0x02);
 108
 109         /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
 110
 111         regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
 112         pci_write_config8(dev, 0x57, regm);
 113
 114         regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
 115         pci_write_config8(dev, 0x61, regm);
 116
 117         regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
 118         pci_write_config8(dev, 0x62, regm);
 119
 120         regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
 121         pci_write_config8(dev, 0xe6, regm);
 122
 123         regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
 124
 125         /*
 126          * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
 127          * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
 128          * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
 129          */
 130         if (regm3 == 0xff)
 131                 regm3 = 0xc0;
 132         else
 133                 regm3 = 0x0;
 134
 135         /* Shadow page F + memhole copy */
 136         regm = pci_read_config8(devfun3, 0x83);
 137         pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
 138 }
 139
 140 static const struct device_operations ctrl_ops = {
 141         .read_resources         = pci_dev_read_resources,
 142         .set_resources          = pci_dev_set_resources,
 143         .enable_resources       = pci_dev_enable_resources,
 144         .enable                 = ctrl_enable,
 145         .init                   = ctrl_init_vt8237r,
 146         .ops_pci                = 0,
 147 };
 148
 149 static const struct pci_driver northbridge_driver __pci_driver = {
 150         .ops    = &ctrl_ops,
 151         .vendor = PCI_VENDOR_ID_VIA,
 152         .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
 153 };