src/southbridge/via/k8t890/host_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25 #include <cbmem.h>
  26 #include <arch/io.h>
  27 #include "k8t890.h"
  28
  29 /* this may be later merged */
  30
  31 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  32 static void host_ctrl_enable_k8t890(struct device *dev)
  33 {
  34         dump_south(dev);
  35
  36         /*
  37          * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
  38          * requests to 3.
  39          */
  40         pci_write_config8(dev, 0xa0, 0x13);
  41
  42         /*
  43          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
  44          * Some bits are set and reserved.
  45          */
  46         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
  47
  48         /* enable NB NVRAM and enable non-posted PCI writes. */
  49         pci_write_config8(dev, 0xa1, 0x8f);
  50         /* Arbitration control, some bits are reserved. */
  51         pci_write_config8(dev, 0xa5, 0x3c);
  52
  53         /* Arbitration control 2 */
  54         pci_write_config8(dev, 0xa6, 0x80);
  55
  56         /* this will be possibly removed, when I figure out
  57          * if the ROM SIP is good, second reason is that the
  58          * unknown bits are AGP related, which are dummy on K8T890
  59          */
  60
  61         writeback(dev, 0xa0, 0x13);     /* Bit4 is reserved! */
  62         writeback(dev, 0xa1, 0x8e);     /* Some bits are reserved. */
  63         writeback(dev, 0xa2, 0x0e);     /* I/O NVRAM base 0xe00-0xeff disabled. */
  64         writeback(dev, 0xa3, 0x31);
  65         writeback(dev, 0xa4, 0x30);
  66
  67         writeback(dev, 0xa5, 0x3c);     /* Some bits reserved. */
  68         writeback(dev, 0xa6, 0x80);     /* Some bits reserved. */
  69         writeback(dev, 0xa7, 0x86);     /* Some bits reserved. */
  70         writeback(dev, 0xa8, 0x7f);     /* Some bits reserved. */
  71         writeback(dev, 0xa9, 0xcf);     /* Some bits reserved. */
  72         writeback(dev, 0xaa, 0x44);
  73         writeback(dev, 0xab, 0x22);
  74         writeback(dev, 0xac, 0x35);     /* Maybe bit0 is read-only? */
  75
  76         writeback(dev, 0xae, 0x22);
  77         writeback(dev, 0xaf, 0x40);
  78         /* b0 is missing. */
  79         writeback(dev, 0xb1, 0x13);
  80         writeback(dev, 0xb4, 0x02);     /* Some bits are reserved. */
  81         writeback(dev, 0xc0, 0x20);
  82         writeback(dev, 0xc1, 0xaa);
  83         writeback(dev, 0xc2, 0xaa);
  84         writeback(dev, 0xc3, 0x02);
  85         writeback(dev, 0xc4, 0x50);
  86         writeback(dev, 0xc5, 0x50);
  87
  88         dump_south(dev);
  89 }
  90
  91 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  92 static void host_ctrl_enable_k8m890(struct device *dev) {
  93
  94         /*
  95          * Set PCI to HT outstanding requests to 03.
  96          * Bit 4 32 AGP ADS Read Outstanding Request Number
  97          */
  98         pci_write_config8(dev, 0xa0, 0x13);
  99
 100         /*
 101          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
 102          */
 103
 104         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
 105
 106         /* Enable NVRAM and enable non-posted PCI writes. */
 107         pci_write_config8(dev, 0xa1, 0x8f);
 108
 109         /* Arbitration control  */
 110         pci_write_config8(dev, 0xa5, 0x3c);
 111
 112         /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
 113         pci_write_config8(dev, 0xa6, 0x83);
 114
 115 }
 116 #if 0
 117 struct cbmem_entry *get_cbmem_toc(void) {
 118                 return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
 119 }
 120 #endif
 121 void set_cbmem_toc(struct cbmem_entry *toc) {
 122                 outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
 123 }
 124
 125 static const struct device_operations host_ctrl_ops_t = {
 126         .read_resources         = pci_dev_read_resources,
 127         .set_resources          = pci_dev_set_resources,
 128         .enable_resources       = pci_dev_enable_resources,
 129         .enable                 = host_ctrl_enable_k8t890,
 130         .ops_pci                = 0,
 131 };
 132
 133 static const struct device_operations host_ctrl_ops_m = {
 134         .read_resources         = pci_dev_read_resources,
 135         .set_resources          = pci_dev_set_resources,
 136         .enable_resources       = pci_dev_enable_resources,
 137         .enable                 = host_ctrl_enable_k8m890,
 138         .ops_pci                = 0,
 139 };
 140
 141 static const struct pci_driver northbridge_driver_t __pci_driver = {
 142         .ops    = &host_ctrl_ops_t,
 143         .vendor = PCI_VENDOR_ID_VIA,
 144         .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
 145 };
 146
 147 static const struct pci_driver northbridge_driver_m __pci_driver = {
 148         .ops    = &host_ctrl_ops_m,
 149         .vendor = PCI_VENDOR_ID_VIA,
 150         .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
 151 };