src/southbridge/via/k8t890/host.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include "k8x8xx.h"
  27
  28 static void host_enable(struct device *dev)
  29 {
  30         /* Multiple function control */
  31         pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
  32
  33         print_debug(" VIA_X_0 device dump:\n");
  34         dump_south(dev);
  35 }
  36
  37
  38 static void host_init(struct device *dev)
  39 {
  40         u8 reg;
  41
  42         /* AGP Capability Header Control */
  43         reg = pci_read_config8(dev, 0x4d);
  44         reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
  45         pci_write_config8(dev, 0x4d, reg);
  46
  47         /* GD Output Stagger Delay */
  48         reg = pci_read_config8(dev, 0x42);
  49         reg |= 0x10; /* AD[31:16] with 1ns */
  50         pci_write_config8(dev, 0x42, reg);
  51
  52         /* AGP Control */
  53         reg = pci_read_config8(dev, 0xbc);
  54         reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
  55         pci_write_config8(dev, 0xbc, reg);
  56
  57 }
  58
  59 static const struct device_operations host_ops_t = {
  60         .read_resources         = pci_dev_read_resources,
  61         .set_resources          = pci_dev_set_resources,
  62         .enable_resources       = pci_dev_enable_resources,
  63         .enable                 = host_enable,
  64         .ops_pci                = 0,
  65 };
  66
  67 static const struct device_operations host_ops_m = {
  68         .read_resources         = pci_dev_read_resources,
  69         .set_resources          = pci_dev_set_resources,
  70         .enable_resources       = pci_dev_enable_resources,
  71         .enable                 = host_enable,
  72         .init                   = host_init,
  73         .ops_pci                = 0,
  74 };
  75
  76 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
  77         .ops    = &host_ops_t,
  78         .vendor = PCI_VENDOR_ID_VIA,
  79         .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR,
  80 };
  81
  82 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
  83         .ops    = &host_ops_m,
  84         .vendor = PCI_VENDOR_ID_VIA,
  85         .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR,
  86 };
  87
  88 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
  89         .ops    = &host_ops_t,
  90         .vendor = PCI_VENDOR_ID_VIA,
  91         .device = PCI_DEVICE_ID_VIA_K8T890CE_0,
  92 };
  93
  94 static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
  95         .ops    = &host_ops_t,
  96         .vendor = PCI_VENDOR_ID_VIA,
  97         .device = PCI_DEVICE_ID_VIA_K8T890CF_0,
  98 };
  99
 100 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 101         .ops    = &host_ops_m,
 102         .vendor = PCI_VENDOR_ID_VIA,
 103         .device = PCI_DEVICE_ID_VIA_K8M890CE_0,
 104 };