2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
5 * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Seems the link and width of HT link needs to be setup too, you need to
23 * generate PCI reset or LDTSTOP to apply.
31 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
32 #define K8T890_NVRAM_IO_BASE 0xf00
33 #define K8T890_MULTIPLE_FN_EN 0x4f
35 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
36 static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
38 /* This functions sets KT890 link frequency and width to same values as
39 * it has been setup on K8 side, by AMD NB init.
40 * This will not work for K8T800_OLD, which has a slightly different
41 * register arrangement (device 3188)
44 u8 k8t890_early_setup_ht(void)
46 u8 awidth, afreq, cldtfreq, reg;
47 u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
50 /* hack, enable NVRAM in chipset */
51 pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
54 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
57 pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
58 reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
60 pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
62 /* check if connected non coherent, initcomplete (find the SB on K8 side) */
64 if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
66 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
68 } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) {
72 #if CONFIG_SOUTHBRIDGE_VIA_K8M800
73 print_debug("K8M800 found at LDT ");
74 #elif CONFIG_SOUTHBRIDGE_VIA_K8T800
75 print_debug("K8T800 found at LDT ");
76 #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO
77 print_debug("K8T800 Pro found at LDT ");
78 #elif CONFIG_SOUTHBRIDGE_VIA_K8M890
79 print_debug("K8M890 found at LDT ");
80 #elif CONFIG_SOUTHBRIDGE_VIA_K8T890
81 print_debug("K8T890 found at LDT ");
83 print_debug_hex8(ldtnr);
85 /* get the maximum widths for both sides */
86 cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
87 cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7;
88 vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7;
89 vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7;
91 width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
92 print_debug(" Agreed on width: ");
93 print_debug_hex8(width);
95 awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
97 /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */
98 width = (width == 0x01) ? 0x11 : 0x00;
100 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width);
102 /* Get programmed HT freq at base 0x89 */
103 cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
104 print_debug(" CPU programmed to HT freq: ");
105 print_debug_hex8(cldtfreq);
107 print_debug(" VIA HT caps: ");
108 vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e);
109 print_debug_hex16(vldtcaps);
111 if (!(vldtcaps & (1 << cldtfreq ))) {
112 die("Chipset does not support desired HT frequency\n");
115 afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
116 pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq);
119 /* no reset needed */
120 if ((width == awidth) && (afreq == cldtfreq)) {
127 static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
130 printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
133 outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
137 outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
141 outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
148 static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
153 *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
157 *old_dword &= ~0xffff;
158 *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
162 *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
166 printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
170 struct cbmem_entry *get_cbmem_toc(void) {
171 return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);