src/southbridge/sis/sis966/sis966_sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   9  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <delay.h>
  29 #include <device/pci.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include "sis966.h"
  33 #include <arch/io.h>
  34
  35 uint8_t SiS_SiS1183_init[68][3]={
  36 {0x04, 0x00, 0x05},
  37 {0x09, 0x00, 0x05},
  38 {0x2C, 0x00, 0x39},
  39 {0x2D, 0x00, 0x10},
  40 {0x2E, 0x00, 0x83},
  41 {0x2F, 0x00, 0x11},
  42 {0x90, 0x00, 0x40},
  43 {0x91, 0x00, 0x00},     // set mode
  44 {0x50, 0x00, 0xA2},
  45 {0x52, 0x00, 0xA2},
  46 {0x55, 0x00, 0x96},
  47 {0x52, 0x00, 0xA2},
  48 {0x55, 0xF7, 0x00},
  49 {0x56, 0x00, 0xC0},
  50 {0x57, 0x00, 0x14},
  51 {0x67, 0x00, 0x28},
  52 {0x81, 0x00, 0xB3},
  53 {0x82, 0x00, 0x72},
  54 {0x83, 0x00, 0x40},
  55 {0x85, 0x00, 0xB3},
  56 {0x86, 0x00, 0x72},
  57 {0x87, 0x00, 0x40},
  58 {0x88, 0x00, 0xDE},      // after set mode
  59 {0x89, 0x00, 0xB3},
  60 {0x8A, 0x00, 0x72},
  61 {0x8B, 0x00, 0x40},
  62 {0x8C, 0x00, 0xDE},
  63 {0x8D, 0x00, 0xB3},
  64 {0x8E, 0x00, 0x92},
  65 {0x8F, 0x00, 0x40},
  66 {0x93, 0x00, 0x00},
  67 {0x94, 0x00, 0x80},
  68 {0x95, 0x00, 0x08},
  69 {0x96, 0x00, 0x80},
  70 {0x97, 0x00, 0x08},
  71 {0x9C, 0x00, 0x80},
  72 {0x9D, 0x00, 0x08},
  73 {0x9E, 0x00, 0x80},
  74 {0x9F, 0x00, 0x08},
  75 {0xA0, 0x00, 0x15},
  76 {0xA1, 0x00, 0x15},
  77 {0xA2, 0x00, 0x15},
  78 {0xA3, 0x00, 0x15},
  79
  80
  81 {0xD8, 0xFE, 0x01},     // Com reset
  82 {0xC8, 0xFE, 0x01},
  83 {0xE8, 0xFE, 0x01},
  84 {0xF8, 0xFE, 0x01},
  85
  86 {0xD8, 0xFE, 0x00},     // Com reset
  87 {0xC8, 0xFE, 0x00},
  88 {0xE8, 0xFE, 0x00},
  89 {0xF8, 0xFE, 0x00},
  90
  91
  92 {0xC4, 0xFF, 0xFF},    // Clear status
  93 {0xC5, 0xFF, 0xFF},
  94 {0xC6, 0xFF, 0xFF},
  95 {0xC7, 0xFF, 0xFF},
  96 {0xD4, 0xFF, 0xFF},
  97 {0xD5, 0xFF, 0xFF},
  98 {0xD6, 0xFF, 0xFF},
  99 {0xD7, 0xFF, 0xFF},
 100 {0xE4, 0xFF, 0xFF},    // Clear status
 101 {0xE5, 0xFF, 0xFF},
 102 {0xE6, 0xFF, 0xFF},
 103 {0xE7, 0xFF, 0xFF},
 104 {0xF4, 0xFF, 0xFF},
 105 {0xF5, 0xFF, 0xFF},
 106 {0xF6, 0xFF, 0xFF},
 107 {0xF7, 0xFF, 0xFF},
 108
 109 {0x00, 0x00, 0x00}                                      //End of table
 110 };
 111
 112 static void sata_init(struct device *dev)
 113 {
 114         struct southbridge_sis_sis966_config *conf;
 115
 116
 117
 118         conf = dev->chip_info;
 119         print_debug("SATA_INIT:---------->\n");
 120
 121 //-------------- enable IDE (SiS1183) -------------------------
 122 {
 123         uint8_t  temp8;
 124         int i=0;
 125         while(SiS_SiS1183_init[i][0] != 0)
 126         {
 127                 temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
 128                 temp8 &= SiS_SiS1183_init[i][1];
 129                 temp8 |= SiS_SiS1183_init[i][2];
 130                 pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
 131                 i++;
 132         };
 133 }
 134 //-----------------------------------------------------------
 135
 136 {
 137 uint32_t i,j;
 138 uint32_t temp32;
 139
 140 for (i=0;i<10;i++){
 141    temp32=0;
 142    temp32= pci_read_config32(dev, 0xC0);
 143    for ( j=0;j<0xFFFF;j++);
 144    printk_debug("status= %x\n",temp32);
 145    if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
 146 }
 147
 148 }
 149
 150 #if DEBUG_SATA
 151 {
 152         int i;
 153
 154         print_debug("****** SATA PCI config ******");
 155         print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 156
 157         for(i=0;i<0xff;i+=4){
 158                 if((i%16)==0){
 159                         print_debug("\r\n");
 160                         print_debug_hex8(i);
 161                         print_debug(": ");
 162                 }
 163                 print_debug_hex32(pci_read_config32(dev,i));
 164                 print_debug("  ");
 165         }
 166         print_debug("\r\n");
 167 }
 168 #endif
 169
 170         print_debug("SATA_INIT:<----------\n");
 171
 172 }
 173
 174 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 175 {
 176         pci_write_config32(dev, 0x40,
 177                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 178 }
 179 static struct pci_operations lops_pci = {
 180         .set_subsystem  = lpci_set_subsystem,
 181 };
 182
 183 static struct device_operations sata_ops = {
 184         .read_resources = pci_dev_read_resources,
 185         .set_resources  = pci_dev_set_resources,
 186         .enable_resources       = pci_dev_enable_resources,
 187 //      .enable         = sis966_enable,
 188         .init           = sata_init,
 189         .scan_bus       = 0,
 190         .ops_pci        = &lops_pci,
 191 };
 192
 193 static const struct pci_driver sata0_driver __pci_driver = {
 194         .ops    = &sata_ops,
 195         .vendor = PCI_VENDOR_ID_SIS,
 196         .device = PCI_DEVICE_ID_SIS_SIS966_SATA,
 197 };