2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2004 Tyan Computer
7 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
8 * Copyright (C) 2006,2007 AMD
9 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
10 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
11 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #include <console/console.h>
29 #include <device/device.h>
30 #include <device/pci.h>
31 #include <device/pnp.h>
32 #include <device/pci_ids.h>
33 #include <device/pci_ops.h>
34 #include <pc80/mc146818rtc.h>
35 #include <pc80/isa-dma.h>
38 #include <arch/ioapic.h>
39 #include <cpu/x86/lapic.h>
42 #include <pc80/keyboard.h>
47 #define PREVIOUS_POWER_STATE 0x7A
49 #define MAINBOARD_POWER_OFF 0
50 #define MAINBOARD_POWER_ON 1
51 #define SLOW_CPU_OFF 0
52 #define SLOW_CPU__ON 1
54 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
55 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
58 static void lpc_common_init(device_t dev)
63 /* IO APIC initialization */
64 byte = pci_read_config8(dev, 0x74);
65 byte |= (1<<0); // enable APIC
66 pci_write_config8(dev, 0x74, byte);
67 ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
69 setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
72 static void lpc_slave_init(device_t dev)
78 static void lpc_usb_legacy_init(device_t dev)
82 acpi_base = (pci_read_config8(dev,0x75) << 8);
84 outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
85 outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
88 static void lpc_init(device_t dev)
95 printk(BIOS_DEBUG, "LPC_INIT -------->\n");
98 lpc_usb_legacy_init(dev);
101 /* power after power fail */
104 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
105 get_option(&on, "power_on_after_fail");
106 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
111 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
112 printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
114 /* Throttle the CPU speed down for testing */
116 get_option(&on, "slow_cpu");
120 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
121 outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
122 dword = inl(pm10_bar + 0x10);
124 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
125 (on*12)+(on>>1),(on&1)*5);
128 /* Enable Error reporting */
129 /* Set up sync flood detected */
130 byte = pci_read_config8(dev, 0x47);
132 pci_write_config8(dev, 0x47, byte);
134 /* Set up NMI on errors */
135 byte = inb(0x70); // RTC70
137 nmi_option = NMI_OFF;
138 get_option(&nmi_option, "nmi");
140 byte &= ~(1 << 7); /* set NMI */
142 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
144 if( byte != byte_old) {
148 /* Initialize the real time clock */
151 /* Initialize isa dma */
154 printk(BIOS_DEBUG, "LPC_INIT <--------\n");
157 static void sis966_lpc_read_resources(device_t dev)
159 struct resource *res;
161 /* Get the normal pci resources of this device */
162 pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
164 /* Add an extra subtractive resource for both memory and I/O. */
165 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
168 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
169 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
171 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
172 res->base = 0xff800000;
173 res->size = 0x00800000; /* 8 MB for flash */
174 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
175 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
177 res = new_resource(dev, 3); /* IOAPIC */
178 res->base = 0xfec00000;
179 res->size = 0x00001000;
180 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
184 * @brief Enable resources for children devices
186 * @param dev the device whos children's resources are to be enabled
188 * This function is call by the global enable_resources() indirectly via the
189 * device_operation::enable_resources() method of devices.
191 * Indirect mutual recursion:
192 * enable_childrens_resources() -> enable_resources()
193 * enable_resources() -> device_operation::enable_resources()
194 * device_operation::enable_resources() -> enable_children_resources()
196 static void sis966_lpc_enable_childrens_resources(device_t dev)
199 uint32_t reg, reg_var[4];
203 reg = pci_read_config32(dev, 0xa0);
205 for (link = 0; link < dev->links; link++) {
207 for (child = dev->link[link].children; child; child = child->sibling) {
208 enable_resources(child);
209 if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
210 for(i=0;i<child->resources;i++) {
211 struct resource *res;
212 unsigned long base, end; // don't need long long
213 res = &child->resource[i];
214 if(!(res->flags & IORESOURCE_IO)) continue;
216 end = resource_end(res);
217 printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
220 reg |= (1<<0); break;
222 reg |= (1<<1); break;
223 case 0x378: // Parallal 1
224 reg |= (1<<24); break;
226 reg |= (1<<20); break;
227 case 0x220: // Aduio 0
228 reg |= (1<<8); break;
229 case 0x300: // Midi 0
230 reg |= (1<<12); break;
232 if( (base == 0x290) || (base >= 0x400)) {
233 if(var_num>=4) continue; // only 4 var ; compact them ?
234 reg |= (1<<(28+var_num));
235 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
241 pci_write_config32(dev, 0xa0, reg);
242 for(i=0;i<var_num;i++) {
243 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
249 static void sis966_lpc_enable_resources(device_t dev)
251 pci_dev_enable_resources(dev);
252 sis966_lpc_enable_childrens_resources(dev);
255 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
257 pci_write_config32(dev, 0x40,
258 ((device & 0xffff) << 16) | (vendor & 0xffff));
261 static struct pci_operations lops_pci = {
262 .set_subsystem = lpci_set_subsystem,
265 static struct device_operations lpc_ops = {
266 .read_resources = sis966_lpc_read_resources,
267 .set_resources = pci_dev_set_resources,
268 .enable_resources = sis966_lpc_enable_resources,
270 .scan_bus = scan_static_bus,
271 // .enable = sis966_enable,
272 .ops_pci = &lops_pci,
274 static const struct pci_driver lpc_driver __pci_driver = {
276 .vendor = PCI_VENDOR_ID_SIS,
277 .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
280 static struct device_operations lpc_slave_ops = {
281 .read_resources = sis966_lpc_read_resources,
282 .set_resources = pci_dev_set_resources,
283 .enable_resources = pci_dev_enable_resources,
284 .init = lpc_slave_init,
285 // .enable = sis966_enable,
286 .ops_pci = &lops_pci,