src/southbridge/sis/sis966/sis966_lpc.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  11  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #include <console/console.h>
  29 #include <device/device.h>
  30 #include <device/pci.h>
  31 #include <device/pnp.h>
  32 #include <device/pci_ids.h>
  33 #include <device/pci_ops.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <pc80/isa-dma.h>
  36 #include <bitops.h>
  37 #include <arch/io.h>
  38 #include <cpu/x86/lapic.h>
  39 #include "sis966.h"
  40 #include <pc80/keyboard.h>
  41
  42 #define NMI_OFF 0
  43
  44 struct ioapicreg {
  45         unsigned int reg;
  46         unsigned int value_low, value_high;
  47 };
  48
  49 static struct ioapicreg ioapicregvalues[] = {
  50 #define ALL             (0xff << 24)
  51 #define NONE            (0)
  52 #define DISABLED        (1 << 16)
  53 #define ENABLED         (0 << 16)
  54 #define TRIGGER_EDGE    (0 << 15)
  55 #define TRIGGER_LEVEL   (1 << 15)
  56 #define POLARITY_HIGH   (0 << 13)
  57 #define POLARITY_LOW    (1 << 13)
  58 #define PHYSICAL_DEST   (0 << 11)
  59 #define LOGICAL_DEST    (1 << 11)
  60 #define ExtINT          (7 << 8)
  61 #define NMI             (4 << 8)
  62 #define SMI             (2 << 8)
  63 #define INT             (1 << 8)
  64         /* IO-APIC virtual wire mode configuration */
  65         /* mask, trigger, polarity, destination, delivery, vector */
  66         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  67         {   1, DISABLED, NONE},
  68         {   2, DISABLED, NONE},
  69         {   3, DISABLED, NONE},
  70         {   4, DISABLED, NONE},
  71         {   5, DISABLED, NONE},
  72         {   6, DISABLED, NONE},
  73         {   7, DISABLED, NONE},
  74         {   8, DISABLED, NONE},
  75         {   9, DISABLED, NONE},
  76         {  10, DISABLED, NONE},
  77         {  11, DISABLED, NONE},
  78         {  12, DISABLED, NONE},
  79         {  13, DISABLED, NONE},
  80         {  14, DISABLED, NONE},
  81         {  15, DISABLED, NONE},
  82         {  16, DISABLED, NONE},
  83         {  17, DISABLED, NONE},
  84         {  18, DISABLED, NONE},
  85         {  19, DISABLED, NONE},
  86         {  20, DISABLED, NONE},
  87         {  21, DISABLED, NONE},
  88         {  22, DISABLED, NONE},
  89         {  23, DISABLED, NONE},
  90         /* Be careful and don't write past the end... */
  91 };
  92
  93 static void setup_ioapic(unsigned long ioapic_base)
  94 {
  95         int i;
  96         unsigned long value_low, value_high;
  97 //      unsigned long ioapic_base = 0xfec00000;
  98         volatile unsigned long *l;
  99         struct ioapicreg *a = ioapicregvalues;
 100
 101         ioapicregvalues[0].value_high = lapicid()<<(56-32);
 102
 103         l = (unsigned long *) ioapic_base;
 104
 105         for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 106              i++, a++) {
 107                 l[0] = (a->reg * 2) + 0x10;
 108                 l[4] = a->value_low;
 109                 value_low = l[4];
 110                 l[0] = (a->reg *2) + 0x11;
 111                 l[4] = a->value_high;
 112                 value_high = l[4];
 113                 if ((i==0) && (value_low == 0xffffffff)) {
 114                         printk_warning("IO APIC not responding.\n");
 115                         return;
 116                 }
 117                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
 118                             a->reg, a->value_low, a->value_high);
 119         }
 120 }
 121
 122 // 0x7a or e3
 123 #define PREVIOUS_POWER_STATE    0x7A
 124
 125 #define MAINBOARD_POWER_OFF     0
 126 #define MAINBOARD_POWER_ON      1
 127 #define SLOW_CPU_OFF    0
 128 #define SLOW_CPU__ON    1
 129
 130 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 131 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL     MAINBOARD_POWER_ON
 132 #endif
 133
 134 static void lpc_common_init(device_t dev)
 135 {
 136         uint8_t byte;
 137         uint32_t dword;
 138
 139         /* IO APIC initialization */
 140         byte = pci_read_config8(dev, 0x74);
 141         byte |= (1<<0); // enable APIC
 142         pci_write_config8(dev, 0x74, byte);
 143         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 144
 145         setup_ioapic(dword);
 146
 147 }
 148
 149 static void lpc_slave_init(device_t dev)
 150 {
 151         lpc_common_init(dev);
 152 }
 153
 154
 155 static void lpc_usb_legacy_init(device_t dev)
 156 {
 157     uint16_t acpi_base;
 158
 159     acpi_base = (pci_read_config8(dev,0x75) << 8);
 160
 161     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
 162     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
 163 }
 164
 165 static void lpc_init(device_t dev)
 166 {
 167          uint8_t byte;
 168          uint8_t byte_old;
 169          int on;
 170          int nmi_option;
 171
 172         printk_debug("LPC_INIT -------->\n");
 173         init_pc_keyboard(0x60, 0x64, 0);
 174
 175         lpc_usb_legacy_init(dev);
 176          lpc_common_init(dev);
 177
 178         /* power after power fail */
 179
 180
 181         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 182         get_option(&on, "power_on_after_fail");
 183         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 184         byte &= ~0x40;
 185         if (!on) {
 186                 byte |= 0x40;
 187         }
 188         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 189         printk_info("set power %s after power fail\n", on?"on":"off");
 190
 191         /* Throttle the CPU speed down for testing */
 192         on = SLOW_CPU_OFF;
 193         get_option(&on, "slow_cpu");
 194         if(on) {
 195                 uint16_t pm10_bar;
 196                 uint32_t dword;
 197                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 198                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 199                 dword = inl(pm10_bar + 0x10);
 200                 on = 8-on;
 201                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 202                                 (on*12)+(on>>1),(on&1)*5);
 203         }
 204
 205         /* Enable Error reporting */
 206         /* Set up sync flood detected */
 207         byte = pci_read_config8(dev, 0x47);
 208         byte |= (1 << 1);
 209         pci_write_config8(dev, 0x47, byte);
 210
 211         /* Set up NMI on errors */
 212         byte = inb(0x70); // RTC70
 213         byte_old = byte;
 214         nmi_option = NMI_OFF;
 215         get_option(&nmi_option, "nmi");
 216         if (nmi_option) {
 217                 byte &= ~(1 << 7); /* set NMI */
 218         } else {
 219                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 220         }
 221         if( byte != byte_old) {
 222                 outb(0x70, byte);
 223         }
 224
 225         /* Initialize the real time clock */
 226         rtc_init(0);
 227
 228         /* Initialize isa dma */
 229         isa_dma_init();
 230
 231         printk_debug("LPC_INIT <--------\n");
 232 }
 233
 234 static void sis966_lpc_read_resources(device_t dev)
 235 {
 236         struct resource *res;
 237         unsigned long index;
 238
 239         /* Get the normal pci resources of this device */
 240         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 241
 242         /* Add an extra subtractive resource for both memory and I/O */
 243         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 244         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 245
 246         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 247         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 248
 249 }
 250
 251 /**
 252  * @brief Enable resources for children devices
 253  *
 254  * @param dev the device whos children's resources are to be enabled
 255  *
 256  * This function is call by the global enable_resources() indirectly via the
 257  * device_operation::enable_resources() method of devices.
 258  *
 259  * Indirect mutual recursion:
 260  *      enable_childrens_resources() -> enable_resources()
 261  *      enable_resources() -> device_operation::enable_resources()
 262  *      device_operation::enable_resources() -> enable_children_resources()
 263  */
 264 static void sis966_lpc_enable_childrens_resources(device_t dev)
 265 {
 266         unsigned link;
 267         uint32_t reg, reg_var[4];
 268         int i;
 269         int var_num = 0;
 270
 271         reg = pci_read_config32(dev, 0xa0);
 272
 273         for (link = 0; link < dev->links; link++) {
 274                 device_t child;
 275                 for (child = dev->link[link].children; child; child = child->sibling) {
 276                         enable_resources(child);
 277                         if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 278                                 for(i=0;i<child->resources;i++) {
 279                                         struct resource *res;
 280                                         unsigned long base, end; // don't need long long
 281                                         res = &child->resource[i];
 282                                         if(!(res->flags & IORESOURCE_IO)) continue;
 283                                         base = res->base;
 284                                         end = resource_end(res);
 285                                         printk_debug("sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 286                                         switch(base) {
 287                                         case 0x3f8: // COM1
 288                                                 reg |= (1<<0);  break;
 289                                         case 0x2f8: // COM2
 290                                                 reg |= (1<<1);  break;
 291                                         case 0x378: // Parallal 1
 292                                                 reg |= (1<<24); break;
 293                                         case 0x3f0: // FD0
 294                                                 reg |= (1<<20); break;
 295                                         case 0x220:  // Aduio 0
 296                                                 reg |= (1<<8);  break;
 297                                         case 0x300:  // Midi 0
 298                                                 reg |= (1<<12); break;
 299                                         }
 300                                         if( (base == 0x290) || (base >= 0x400)) {
 301                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 302                                                 reg |= (1<<(28+var_num));
 303                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 304                                         }
 305                                 }
 306                         }
 307                 }
 308         }
 309         pci_write_config32(dev, 0xa0, reg);
 310         for(i=0;i<var_num;i++) {
 311                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 312         }
 313
 314
 315 }
 316
 317 static void sis966_lpc_enable_resources(device_t dev)
 318 {
 319         pci_dev_enable_resources(dev);
 320         sis966_lpc_enable_childrens_resources(dev);
 321 }
 322
 323 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 324 {
 325         pci_write_config32(dev, 0x40,
 326                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 327 }
 328
 329 static struct pci_operations lops_pci = {
 330         .set_subsystem  = lpci_set_subsystem,
 331 };
 332
 333 static struct device_operations lpc_ops  = {
 334         .read_resources = sis966_lpc_read_resources,
 335         .set_resources  = pci_dev_set_resources,
 336         .enable_resources       = sis966_lpc_enable_resources,
 337         .init           = lpc_init,
 338         .scan_bus       = scan_static_bus,
 339 //      .enable         = sis966_enable,
 340         .ops_pci        = &lops_pci,
 341 };
 342 static const struct pci_driver lpc_driver __pci_driver = {
 343         .ops    = &lpc_ops,
 344         .vendor = PCI_VENDOR_ID_SIS,
 345         .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
 346 };
 347
 348 static struct device_operations lpc_slave_ops  = {
 349         .read_resources = sis966_lpc_read_resources,
 350         .set_resources  = pci_dev_set_resources,
 351         .enable_resources       = pci_dev_enable_resources,
 352         .init           = lpc_slave_init,
 353 //      .enable         = sis966_enable,
 354         .ops_pci        = &lops_pci,
 355 };