2 * (C) Copyright 2004-2005 Nick Barker <nick.barker@btinternet.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ops.h>
24 #include <device/pci_ids.h>
25 #include <console/console.h>
26 #include <device/cardbus.h>
30 static int enable_cf_boot = 0;
31 static unsigned int cf_base;
33 static void rl5c476_init(device_t dev)
38 /* cardbus controller function 1 for CF Socket */
39 printk_debug("Ricoh RL5c476: Initializing.\n");
41 printk_debug("CF Base = %0x\n",cf_base);
43 /* misc control register */
44 pci_write_config16(dev,0x82,0x00a0);
46 /* set up second slot as compact flash port if asked to do so */
48 if (!enable_cf_boot) {
49 printk_debug("CF boot not enabled.\n");
53 if (PCI_FUNC(dev->path.pci.devfn) != 1) {
54 // Only configure if second CF slot.
58 /* make sure isa interrupts are enabled */
59 pci_write_config16(dev,0x3e,0x0780);
61 /* pick up where 16 bit card control structure is
62 * (0x800 bytes into config structure)
64 base = (unsigned char *)pci_read_config32(dev,0x10);
65 pc16 = (pc16reg_t *)(base + 0x800);
67 /* disable memory and io windows and turn off socket power */
70 /* disable irq lines */
73 /* disable memory and I/O windows */
76 /* reset card, configure for I/O and set IRQ line */
79 /* set io window 0 for 1e0 - 1ef */
80 /* NOTE: This now sets CF up on a contiguous I/O window of
81 * 16 bytes, 0x1e0 to 0x1ef.
82 * Be warned that this is not a standard IDE address as
83 * automatically detected by the likes of FILO, and would need
84 * patching to recognise these addresses as an IDE drive.
86 * An earlier version of this driver set up 2 I/O windows to
87 * emulate the expected addresses for IDE2, however the PCMCIA
88 * package within Linux then could not re-initialize the
89 * device as it tried to take control of it. So I believe it is
90 * easier to patch Filo or the like to pick up this drive
91 * rather than playing silly games as the kernel tries to
94 * Nonetheless, FILO needs a special option enabled to boot
95 * from this configuration, and it needs to clean up
96 * afterwards. Please refer to FILO documentation and source
97 * code for more details.
118 /* set up CF config window */
119 pc16->smpga0 = cf_base>>24;
120 pc16->smsth0 = (cf_base>>20)&0x0f;
121 pc16->smstl0 = (cf_base>>12)&0xff;
122 pc16->smsph0 = ((cf_base>>20)&0x0f) | 0x80;
123 pc16->smspl0 = (cf_base>>12)&0xff;
128 /* set I/O width for Auto Data width */
132 /* enable I/O window 0 and 1 */
137 /* apply power and enable outputs */
140 // delay could be optimised, but this works
146 /* 16 bit CF always have first config byte at 0x200 into
147 * Config structure, but CF+ may not according to spec -
148 * should locate through reading tuple data, but this should
152 cptr = (unsigned char *)(cf_base + 0x200);
153 printk_debug("CF Config = %x\n",*cptr);
155 /* Set CF to decode 16 IO bytes on any 16 byte boundary -
156 * rely on the io windows of the bridge set up above to
157 * map those bytes into the addresses for IDE controller 3
158 * (0x1e8 - 0x1ef and 0x3ed - 0x3ee)
163 void rl5c476_read_resources(device_t dev)
166 struct resource *resource;
168 /* For CF socket we need an extra memory window for
169 * the control structure of the CF itself
171 if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
172 /* fake index as it isn't in PCI config space */
173 resource = new_resource(dev, 1);
174 resource->flags |= IORESOURCE_MEM ;
175 resource->size = 0x1000;
176 resource->align = resource->gran = 12;
177 resource->limit= 0xffff0000;
179 cardbus_read_resources(dev);
182 void rl5c476_set_resources(device_t dev)
184 struct resource *resource;
185 printk_debug("%s In set resources \n",dev_path(dev));
186 if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
187 resource = find_resource(dev,1);
188 if( !(resource->flags & IORESOURCE_STORED) ){
189 resource->flags |= IORESOURCE_STORED ;
190 printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base);
191 cf_base = resource->base;
195 pci_dev_set_resources(dev);
199 static struct device_operations ricoh_rl5c476_ops = {
200 .read_resources = rl5c476_read_resources,
201 .set_resources = rl5c476_set_resources,
202 .enable_resources = cardbus_enable_resources,
203 .init = rl5c476_init,
204 .scan_bus = cardbus_scan_bridge,
207 static const struct pci_driver ricoh_rl5c476_driver __pci_driver = {
208 .ops = &ricoh_rl5c476_ops,
209 .vendor = PCI_VENDOR_ID_RICOH,
210 .device = PCI_DEVICE_ID_RICOH_RL5C476,
213 void southbridge_init(device_t dev)
216 struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info;
217 enable_cf_boot = conf->enable_cf;
221 struct chip_operations southbridge_ricoh_rl5c476_ops = {
222 CHIP_NAME("Ricoh RL5C476 CardBus Controller")
223 .enable_dev = southbridge_init,