src/southbridge/nvidia/mcp55/mcp55_nic.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <console/console.h>
  25 #include <device/device.h>
  26 #include <device/smbus.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/pci_ops.h>
  30 #include <arch/io.h>
  31 #include "mcp55.h"
  32
  33 static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
  34 {
  35         uint32_t dword;
  36         unsigned loop = 0x100;
  37         writel(0x8000, base+0x190); //Clear MDIO lock bit
  38         mdelay(1);
  39         dword = readl(base+0x190);
  40         if(dword & (1<<15)) return -1;
  41
  42         writel(1, base+0x180);
  43         writel((phy_addr<<5) | (phy_reg),base + 0x190);
  44         do{
  45                 dword = readl(base + 0x190);
  46                 if(--loop==0) return -4;
  47         } while ((dword & (1<<15)) );
  48
  49         dword = readl(base + 0x180);
  50         if(dword & 1) return -3;
  51
  52         dword = readl(base + 0x194);
  53
  54         return dword;
  55
  56 }
  57
  58 static int phy_detect(uint8_t *base)
  59 {
  60         uint32_t dword;
  61         int i;
  62         int val;
  63         unsigned id;
  64         dword = readl(base+0x188);
  65         dword &= ~(1<<20);
  66         writel(dword, base+0x188);
  67
  68         phy_read(base, 0, 1);
  69
  70         for(i=1; i<=32; i++) {
  71                 int phyaddr = i & 0x1f;
  72                 val = phy_read(base, phyaddr, 1);
  73                 if(val<0) continue;
  74                 if((val & 0xffff) == 0xfffff) continue;
  75                 if((val & 0xffff) == 0) continue;
  76                 if(!(val & 1)) {
  77                         break; // Ethernet PHY
  78                 }
  79                 val = phy_read(base, phyaddr, 3);
  80                 if (val < 0 || val == 0xffff) continue;
  81                 id = val & 0xfc00;
  82                 val = phy_read(base, phyaddr, 2);
  83                 if (val < 0 || val == 0xffff) continue;
  84                 id |= ((val & 0xffff)<<16);
  85                 printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
  86 //              if((id == 0xe0180000) || (id==0x0032cc00))
  87                         break;
  88         }
  89
  90         if(i>32) {
  91                 printk_debug("MCP55 MAC PHY not found\n");
  92         }
  93
  94 }
  95 static void nic_init(struct device *dev)
  96 {
  97         uint32_t dword, old;
  98         uint32_t mac_h, mac_l;
  99         int eeprom_valid = 0;
 100         struct southbridge_nvidia_mcp55_config *conf;
 101
 102         static uint32_t nic_index = 0;
 103
 104         uint8_t *base;
 105         struct resource *res;
 106
 107         res = find_resource(dev, 0x10);
 108
 109         if(!res) return;
 110
 111         base = res->base;
 112
 113         phy_detect(base);
 114
 115 #define NvRegPhyInterface       0xC0
 116 #define PHY_RGMII       0x10000000
 117
 118         writel(PHY_RGMII, base + NvRegPhyInterface);
 119
 120         conf = dev->chip_info;
 121
 122         if(conf->mac_eeprom_smbus != 0) {
 123 //      read MAC address from EEPROM at first
 124                 struct device *dev_eeprom;
 125                 dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
 126
 127                 if(dev_eeprom) {
 128                 //      if that is valid we will use that
 129                         unsigned char dat[6];
 130                         int status;
 131                         int i;
 132                         for(i=0;i<6;i++) {
 133                                 status = smbus_read_byte(dev_eeprom, i);
 134                                 if(status < 0) break;
 135                                 dat[i] = status & 0xff;
 136                         }
 137                         if(status >= 0) {
 138                                 mac_l = 0;
 139                                 for(i=3;i>=0;i--) {
 140                                         mac_l <<= 8;
 141                                         mac_l += dat[i];
 142                                 }
 143                                 if(mac_l != 0xffffffff) {
 144                                         mac_l += nic_index;
 145                                         mac_h = 0;
 146                                         for(i=5;i>=4;i--) {
 147                                                 mac_h <<= 8;
 148                                                 mac_h += dat[i];
 149                                         }
 150                                         eeprom_valid = 1;
 151                                 }
 152                         }
 153                 }
 154         }
 155 //      if that is invalid we will read that from romstrap
 156         if(!eeprom_valid) {
 157                 unsigned long mac_pos;
 158                 mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
 159                 mac_l = readl(mac_pos) + nic_index; // overflow?
 160                 mac_h = readl(mac_pos + 4);
 161
 162         }
 163 #if 1
 164 //      set that into NIC MMIO
 165 #define NvRegMacAddrA   0xA8
 166 #define NvRegMacAddrB   0xAC
 167         writel(mac_l, base + NvRegMacAddrA);
 168         writel(mac_h, base + NvRegMacAddrB);
 169 #else
 170 //      set that into NIC
 171         pci_write_config32(dev, 0xa8, mac_l);
 172         pci_write_config32(dev, 0xac, mac_h);
 173 #endif
 174
 175         nic_index++;
 176
 177 #if CONFIG_PCI_ROM_RUN == 1
 178         pci_dev_init(dev);// it will init option rom
 179 #endif
 180
 181 }
 182
 183 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 184 {
 185         pci_write_config32(dev, 0x40,
 186                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 187 }
 188
 189 static struct pci_operations lops_pci = {
 190         .set_subsystem  = lpci_set_subsystem,
 191 };
 192
 193 static struct device_operations nic_ops  = {
 194         .read_resources = pci_dev_read_resources,
 195         .set_resources  = pci_dev_set_resources,
 196         .enable_resources       = pci_dev_enable_resources,
 197         .init           = nic_init,
 198         .scan_bus       = 0,
 199 //      .enable         = mcp55_enable,
 200         .ops_pci        = &lops_pci,
 201 };
 202 static const struct pci_driver nic_driver __pci_driver = {
 203         .ops    = &nic_ops,
 204         .vendor = PCI_VENDOR_ID_NVIDIA,
 205         .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC,
 206 };
 207 static const struct pci_driver nic_bridge_driver __pci_driver = {
 208         .ops    = &nic_ops,
 209         .vendor = PCI_VENDOR_ID_NVIDIA,
 210         .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE,
 211 };