2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/smbus.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
29 #include <device/pci_ops.h>
34 static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
37 unsigned loop = 0x100;
38 writel(0x8000, base+0x190); //Clear MDIO lock bit
40 dword = readl(base+0x190);
41 if(dword & (1<<15)) return -1;
43 writel(1, base+0x180);
44 writel((phy_addr<<5) | (phy_reg),base + 0x190);
46 dword = readl(base + 0x190);
47 if(--loop==0) return -4;
48 } while ((dword & (1<<15)) );
50 dword = readl(base + 0x180);
51 if(dword & 1) return -3;
53 dword = readl(base + 0x194);
59 static void phy_detect(uint8_t *base)
65 dword = readl(base+0x188);
67 writel(dword, base+0x188);
71 for(i=1; i<=32; i++) {
72 int phyaddr = i & 0x1f;
73 val = phy_read(base, phyaddr, 1);
75 if((val & 0xffff) == 0xfffff) continue;
76 if((val & 0xffff) == 0) continue;
78 break; // Ethernet PHY
80 val = phy_read(base, phyaddr, 3);
81 if (val < 0 || val == 0xffff) continue;
83 val = phy_read(base, phyaddr, 2);
84 if (val < 0 || val == 0xffff) continue;
85 id |= ((val & 0xffff)<<16);
86 printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
87 // if((id == 0xe0180000) || (id==0x0032cc00))
92 printk_debug("MCP55 MAC PHY not found\n");
96 static void nic_init(struct device *dev)
99 uint32_t mac_h, mac_l;
100 int eeprom_valid = 0;
101 struct southbridge_nvidia_mcp55_config *conf;
103 static uint32_t nic_index = 0;
106 struct resource *res;
108 res = find_resource(dev, 0x10);
116 #define NvRegPhyInterface 0xC0
117 #define PHY_RGMII 0x10000000
119 writel(PHY_RGMII, base + NvRegPhyInterface);
121 conf = dev->chip_info;
123 if(conf->mac_eeprom_smbus != 0) {
124 // read MAC address from EEPROM at first
125 struct device *dev_eeprom;
126 dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
129 // if that is valid we will use that
130 unsigned char dat[6];
134 status = smbus_read_byte(dev_eeprom, i);
135 if(status < 0) break;
136 dat[i] = status & 0xff;
144 if(mac_l != 0xffffffff) {
156 // if that is invalid we will read that from romstrap
158 unsigned long mac_pos;
159 mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
160 mac_l = readl(mac_pos) + nic_index; // overflow?
161 mac_h = readl(mac_pos + 4);
165 // set that into NIC MMIO
166 #define NvRegMacAddrA 0xA8
167 #define NvRegMacAddrB 0xAC
168 writel(mac_l, base + NvRegMacAddrA);
169 writel(mac_h, base + NvRegMacAddrB);
172 pci_write_config32(dev, 0xa8, mac_l);
173 pci_write_config32(dev, 0xac, mac_h);
178 #if CONFIG_PCI_ROM_RUN == 1
179 pci_dev_init(dev);// it will init option rom
184 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
186 pci_write_config32(dev, 0x40,
187 ((device & 0xffff) << 16) | (vendor & 0xffff));
190 static struct pci_operations lops_pci = {
191 .set_subsystem = lpci_set_subsystem,
194 static struct device_operations nic_ops = {
195 .read_resources = pci_dev_read_resources,
196 .set_resources = pci_dev_set_resources,
197 .enable_resources = pci_dev_enable_resources,
200 // .enable = mcp55_enable,
201 .ops_pci = &lops_pci,
203 static const struct pci_driver nic_driver __pci_driver = {
205 .vendor = PCI_VENDOR_ID_NVIDIA,
206 .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC,
208 static const struct pci_driver nic_bridge_driver __pci_driver = {
210 .vendor = PCI_VENDOR_ID_NVIDIA,
211 .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE,