src/southbridge/nvidia/mcp55/mcp55_lpc.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pnp.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <pc80/isa-dma.h>
  34 #include <bitops.h>
  35 #include <arch/io.h>
  36 #include <cpu/x86/lapic.h>
  37 #include "mcp55.h"
  38
  39 #define NMI_OFF 0
  40
  41 struct ioapicreg {
  42         unsigned int reg;
  43         unsigned int value_low, value_high;
  44 };
  45
  46 static struct ioapicreg ioapicregvalues[] = {
  47 #define ALL             (0xff << 24)
  48 #define NONE            (0)
  49 #define DISABLED        (1 << 16)
  50 #define ENABLED         (0 << 16)
  51 #define TRIGGER_EDGE    (0 << 15)
  52 #define TRIGGER_LEVEL   (1 << 15)
  53 #define POLARITY_HIGH   (0 << 13)
  54 #define POLARITY_LOW    (1 << 13)
  55 #define PHYSICAL_DEST   (0 << 11)
  56 #define LOGICAL_DEST    (1 << 11)
  57 #define ExtINT          (7 << 8)
  58 #define NMI             (4 << 8)
  59 #define SMI             (2 << 8)
  60 #define INT             (1 << 8)
  61         /* IO-APIC virtual wire mode configuration */
  62         /* mask, trigger, polarity, destination, delivery, vector */
  63         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  64         {   1, DISABLED, NONE},
  65         {   2, DISABLED, NONE},
  66         {   3, DISABLED, NONE},
  67         {   4, DISABLED, NONE},
  68         {   5, DISABLED, NONE},
  69         {   6, DISABLED, NONE},
  70         {   7, DISABLED, NONE},
  71         {   8, DISABLED, NONE},
  72         {   9, DISABLED, NONE},
  73         {  10, DISABLED, NONE},
  74         {  11, DISABLED, NONE},
  75         {  12, DISABLED, NONE},
  76         {  13, DISABLED, NONE},
  77         {  14, DISABLED, NONE},
  78         {  15, DISABLED, NONE},
  79         {  16, DISABLED, NONE},
  80         {  17, DISABLED, NONE},
  81         {  18, DISABLED, NONE},
  82         {  19, DISABLED, NONE},
  83         {  20, DISABLED, NONE},
  84         {  21, DISABLED, NONE},
  85         {  22, DISABLED, NONE},
  86         {  23, DISABLED, NONE},
  87         /* Be careful and don't write past the end... */
  88 };
  89
  90 static void setup_ioapic(unsigned long ioapic_base)
  91 {
  92         int i;
  93         unsigned long value_low, value_high;
  94 //      unsigned long ioapic_base = 0xfec00000;
  95         volatile unsigned long *l;
  96         struct ioapicreg *a = ioapicregvalues;
  97
  98         ioapicregvalues[0].value_high = lapicid()<<(56-32);
  99
 100         l = (unsigned long *) ioapic_base;
 101
 102         for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 103              i++, a++) {
 104                 l[0] = (a->reg * 2) + 0x10;
 105                 l[4] = a->value_low;
 106                 value_low = l[4];
 107                 l[0] = (a->reg *2) + 0x11;
 108                 l[4] = a->value_high;
 109                 value_high = l[4];
 110                 if ((i==0) && (value_low == 0xffffffff)) {
 111                         printk_warning("IO APIC not responding.\n");
 112                         return;
 113                 }
 114                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
 115                             a->reg, a->value_low, a->value_high);
 116         }
 117 }
 118
 119 // 0x7a or e3
 120 #define PREVIOUS_POWER_STATE    0x7A
 121
 122 #define MAINBOARD_POWER_OFF     0
 123 #define MAINBOARD_POWER_ON      1
 124 #define SLOW_CPU_OFF    0
 125 #define SLOW_CPU__ON    1
 126
 127 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 128 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL     MAINBOARD_POWER_ON
 129 #endif
 130
 131 static void lpc_common_init(device_t dev)
 132 {
 133         uint8_t byte;
 134         uint32_t dword;
 135
 136         /* IO APIC initialization */
 137         byte = pci_read_config8(dev, 0x74);
 138         byte |= (1<<0); // enable APIC
 139         pci_write_config8(dev, 0x74, byte);
 140         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 141
 142         setup_ioapic(dword);
 143
 144 }
 145
 146 static void lpc_slave_init(device_t dev)
 147 {
 148         lpc_common_init(dev);
 149 }
 150
 151 #if 0
 152 static void enable_hpet(struct device *dev)
 153 {
 154         unsigned long hpet_address;
 155
 156         pci_write_config32(dev,0x44, 0xfed00001);
 157         hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 158         printk_debug("enabling HPET @0x%x\n", hpet_address);
 159 }
 160 #endif
 161
 162 static void lpc_init(device_t dev)
 163 {
 164         uint8_t byte;
 165         uint8_t byte_old;
 166         int on;
 167         int nmi_option;
 168
 169         lpc_common_init(dev);
 170
 171 #if 0
 172         /* posted memory write enable */
 173         byte = pci_read_config8(dev, 0x46);
 174         pci_write_config8(dev, 0x46, byte | (1<<0));
 175
 176 #endif
 177         /* power after power fail */
 178
 179 #if 1
 180         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 181         get_option(&on, "power_on_after_fail");
 182         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 183         byte &= ~0x40;
 184         if (!on) {
 185                 byte |= 0x40;
 186         }
 187         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 188         printk_info("set power %s after power fail\n", on?"on":"off");
 189 #endif
 190         /* Throttle the CPU speed down for testing */
 191         on = SLOW_CPU_OFF;
 192         get_option(&on, "slow_cpu");
 193         if(on) {
 194                 uint16_t pm10_bar;
 195                 uint32_t dword;
 196                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 197                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 198                 dword = inl(pm10_bar + 0x10);
 199                 on = 8-on;
 200                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 201                                 (on*12)+(on>>1),(on&1)*5);
 202         }
 203
 204 #if 0
 205 // default is enabled
 206         /* Enable Port 92 fast reset */
 207         byte = pci_read_config8(dev, 0xe8);
 208         byte |= ~(1 << 3);
 209         pci_write_config8(dev, 0xe8, byte);
 210 #endif
 211
 212         /* Enable Error reporting */
 213         /* Set up sync flood detected */
 214         byte = pci_read_config8(dev, 0x47);
 215         byte |= (1 << 1);
 216         pci_write_config8(dev, 0x47, byte);
 217
 218         /* Set up NMI on errors */
 219         byte = inb(0x70); // RTC70
 220         byte_old = byte;
 221         nmi_option = NMI_OFF;
 222         get_option(&nmi_option, "nmi");
 223         if (nmi_option) {
 224                 byte &= ~(1 << 7); /* set NMI */
 225         } else {
 226                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 227         }
 228         if( byte != byte_old) {
 229                 outb(0x70, byte);
 230         }
 231
 232         /* Initialize the real time clock */
 233         rtc_init(0);
 234
 235         /* Initialize isa dma */
 236         isa_dma_init();
 237
 238         /* Initialize the High Precision Event Timers */
 239 //      enable_hpet(dev);
 240
 241 }
 242
 243 static void mcp55_lpc_read_resources(device_t dev)
 244 {
 245         struct resource *res;
 246         unsigned long index;
 247
 248         /* Get the normal pci resources of this device */
 249         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 250
 251         /* Add an extra subtractive resource for both memory and I/O */
 252         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 253         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 254
 255         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 256         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 257
 258 }
 259
 260 /**
 261  * @brief Enable resources for children devices
 262  *
 263  * @param dev the device whos children's resources are to be enabled
 264  *
 265  * This function is call by the global enable_resources() indirectly via the
 266  * device_operation::enable_resources() method of devices.
 267  *
 268  * Indirect mutual recursion:
 269  *      enable_childrens_resources() -> enable_resources()
 270  *      enable_resources() -> device_operation::enable_resources()
 271  *      device_operation::enable_resources() -> enable_children_resources()
 272  */
 273 static void mcp55_lpc_enable_childrens_resources(device_t dev)
 274 {
 275         unsigned link;
 276         uint32_t reg, reg_var[4];
 277         int i;
 278         int var_num = 0;
 279
 280         reg = pci_read_config32(dev, 0xa0);
 281
 282         for (link = 0; link < dev->links; link++) {
 283                 device_t child;
 284                 for (child = dev->link[link].children; child; child = child->sibling) {
 285                         enable_resources(child);
 286                         if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 287                                 for(i=0;i<child->resources;i++) {
 288                                         struct resource *res;
 289                                         unsigned long base, end; // don't need long long
 290                                         res = &child->resource[i];
 291                                         if(!(res->flags & IORESOURCE_IO)) continue;
 292                                         base = res->base;
 293                                         end = resource_end(res);
 294                                         printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 295                                         switch(base) {
 296                                         case 0x3f8: // COM1
 297                                                 reg |= (1<<0);  break;
 298                                         case 0x2f8: // COM2
 299                                                 reg |= (1<<1);  break;
 300                                         case 0x378: // Parallal 1
 301                                                 reg |= (1<<24); break;
 302                                         case 0x3f0: // FD0
 303                                                 reg |= (1<<20); break;
 304                                         case 0x220:  // Aduio 0
 305                                                 reg |= (1<<8);  break;
 306                                         case 0x300:  // Midi 0
 307                                                 reg |= (1<<12); break;
 308                                         }
 309                                         if( (base == 0x290) || (base >= 0x400)) {
 310                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 311                                                 reg |= (1<<(28+var_num));
 312                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 313                                         }
 314                                 }
 315                         }
 316                 }
 317         }
 318         pci_write_config32(dev, 0xa0, reg);
 319         for(i=0;i<var_num;i++) {
 320                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 321         }
 322
 323
 324 }
 325
 326 static void mcp55_lpc_enable_resources(device_t dev)
 327 {
 328         pci_dev_enable_resources(dev);
 329         mcp55_lpc_enable_childrens_resources(dev);
 330 }
 331
 332 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 333 {
 334         pci_write_config32(dev, 0x40,
 335                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 336 }
 337
 338 static struct pci_operations lops_pci = {
 339         .set_subsystem  = lpci_set_subsystem,
 340 };
 341
 342 static struct device_operations lpc_ops  = {
 343         .read_resources = mcp55_lpc_read_resources,
 344         .set_resources  = pci_dev_set_resources,
 345         .enable_resources       = mcp55_lpc_enable_resources,
 346         .init           = lpc_init,
 347         .scan_bus       = scan_static_bus,
 348 //      .enable         = mcp55_enable,
 349         .ops_pci        = &lops_pci,
 350 };
 351 static struct pci_driver lpc_driver __pci_driver = {
 352         .ops    = &lpc_ops,
 353         .vendor = PCI_VENDOR_ID_NVIDIA,
 354         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
 355 };
 356
 357 static struct pci_driver lpc_driver_pro __pci_driver = {
 358         .ops    = &lpc_ops,
 359         .vendor = PCI_VENDOR_ID_NVIDIA,
 360         .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
 361 };
 362
 363 static struct pci_driver lpc_driver_lpc2 __pci_driver = {
 364         .ops    = &lpc_ops,
 365         .vendor = PCI_VENDOR_ID_NVIDIA,
 366         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
 367 };
 368 static struct pci_driver lpc_driver_lpc3 __pci_driver = {
 369         .ops    = &lpc_ops,
 370         .vendor = PCI_VENDOR_ID_NVIDIA,
 371         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
 372 };
 373 static struct pci_driver lpc_driver_lpc4 __pci_driver = {
 374         .ops    = &lpc_ops,
 375         .vendor = PCI_VENDOR_ID_NVIDIA,
 376         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
 377 };
 378 static struct pci_driver lpc_driver_lpc5 __pci_driver = {
 379         .ops    = &lpc_ops,
 380         .vendor = PCI_VENDOR_ID_NVIDIA,
 381         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
 382 };
 383 static struct pci_driver lpc_driver_lpc6 __pci_driver = {
 384         .ops    = &lpc_ops,
 385         .vendor = PCI_VENDOR_ID_NVIDIA,
 386         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
 387 };
 388
 389 static struct device_operations lpc_slave_ops  = {
 390         .read_resources = mcp55_lpc_read_resources,
 391         .set_resources  = pci_dev_set_resources,
 392         .enable_resources       = pci_dev_enable_resources,
 393         .init           = lpc_slave_init,
 394 //      .enable         = mcp55_enable,
 395         .ops_pci        = &lops_pci,
 396 };
 397
 398 static struct pci_driver lpc_driver_slave __pci_driver = {
 399         .ops    = &lpc_slave_ops,
 400         .vendor = PCI_VENDOR_ID_NVIDIA,
 401         .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
 402 };