src/southbridge/nvidia/mcp55/mcp55_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pnp.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <pc80/isa-dma.h>
  34 #include <bitops.h>
  35 #include <arch/io.h>
  36 #include <cpu/x86/lapic.h>
  37 #include "mcp55.h"
  38
  39 #define NMI_OFF 0
  40
  41 struct ioapicreg {
  42         unsigned int reg;
  43         unsigned int value_low, value_high;
  44 };
  45
  46 static struct ioapicreg ioapicregvalues[] = {
  47 #define ALL             (0xff << 24)
  48 #define NONE            (0)
  49 #define DISABLED        (1 << 16)
  50 #define ENABLED         (0 << 16)
  51 #define TRIGGER_EDGE    (0 << 15)
  52 #define TRIGGER_LEVEL   (1 << 15)
  53 #define POLARITY_HIGH   (0 << 13)
  54 #define POLARITY_LOW    (1 << 13)
  55 #define PHYSICAL_DEST   (0 << 11)
  56 #define LOGICAL_DEST    (1 << 11)
  57 #define ExtINT          (7 << 8)
  58 #define NMI             (4 << 8)
  59 #define SMI             (2 << 8)
  60 #define INT             (1 << 8)
  61         /* IO-APIC virtual wire mode configuration */
  62         /* mask, trigger, polarity, destination, delivery, vector */
  63         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  64         {   1, DISABLED, NONE},
  65         {   2, DISABLED, NONE},
  66         {   3, DISABLED, NONE},
  67         {   4, DISABLED, NONE},
  68         {   5, DISABLED, NONE},
  69         {   6, DISABLED, NONE},
  70         {   7, DISABLED, NONE},
  71         {   8, DISABLED, NONE},
  72         {   9, DISABLED, NONE},
  73         {  10, DISABLED, NONE},
  74         {  11, DISABLED, NONE},
  75         {  12, DISABLED, NONE},
  76         {  13, DISABLED, NONE},
  77         {  14, DISABLED, NONE},
  78         {  15, DISABLED, NONE},
  79         {  16, DISABLED, NONE},
  80         {  17, DISABLED, NONE},
  81         {  18, DISABLED, NONE},
  82         {  19, DISABLED, NONE},
  83         {  20, DISABLED, NONE},
  84         {  21, DISABLED, NONE},
  85         {  22, DISABLED, NONE},
  86         {  23, DISABLED, NONE},
  87         /* Be careful and don't write past the end... */
  88 };
  89
  90 static void setup_ioapic(unsigned long ioapic_base, int master)
  91 {
  92         int i;
  93         unsigned long value_low, value_high;
  94 //      unsigned long ioapic_base = 0xfec00000;
  95         volatile unsigned long *l;
  96         struct ioapicreg *a = ioapicregvalues;
  97
  98         if (master) {
  99                 ioapicregvalues[0].value_high = lapicid()<<(56-32);
 100                 ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
 101         }
 102         else {
 103                 ioapicregvalues[0].value_high = NONE;
 104                 ioapicregvalues[0].value_low = DISABLED;
 105         }
 106
 107         l = (unsigned long *) ioapic_base;
 108
 109         for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 110              i++, a++) {
 111                 l[0] = (a->reg * 2) + 0x10;
 112                 l[4] = a->value_low;
 113                 value_low = l[4];
 114                 l[0] = (a->reg *2) + 0x11;
 115                 l[4] = a->value_high;
 116                 value_high = l[4];
 117                 if ((i==0) && (value_low == 0xffffffff)) {
 118                         printk_warning("IO APIC not responding.\n");
 119                         return;
 120                 }
 121                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
 122                             a->reg, a->value_low, a->value_high);
 123         }
 124 }
 125
 126 // 0x7a or e3
 127 #define PREVIOUS_POWER_STATE    0x7A
 128
 129 #define MAINBOARD_POWER_OFF     0
 130 #define MAINBOARD_POWER_ON      1
 131 #define SLOW_CPU_OFF            0
 132 #define SLOW_CPU__ON            1
 133
 134 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 135 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 136 #endif
 137
 138 static void lpc_common_init(device_t dev, int master)
 139 {
 140         uint8_t byte;
 141         uint32_t dword;
 142
 143         /* IO APIC initialization */
 144         byte = pci_read_config8(dev, 0x74);
 145         byte |= (1<<0); // enable APIC
 146         pci_write_config8(dev, 0x74, byte);
 147         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 148
 149         setup_ioapic(dword, master);
 150 }
 151
 152 static void lpc_slave_init(device_t dev)
 153 {
 154         lpc_common_init(dev, 0);
 155 }
 156
 157 #if 0
 158 static void enable_hpet(struct device *dev)
 159 {
 160         unsigned long hpet_address;
 161
 162         pci_write_config32(dev,0x44, 0xfed00001);
 163         hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 164         printk_debug("enabling HPET @0x%x\n", hpet_address);
 165 }
 166 #endif
 167
 168 static void lpc_init(device_t dev)
 169 {
 170         uint8_t byte;
 171         uint8_t byte_old;
 172         int on;
 173         int nmi_option;
 174
 175         lpc_common_init(dev, 1);
 176
 177 #if 0
 178         /* posted memory write enable */
 179         byte = pci_read_config8(dev, 0x46);
 180         pci_write_config8(dev, 0x46, byte | (1<<0));
 181 #endif
 182         /* power after power fail */
 183
 184 #if 1
 185         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 186         get_option(&on, "power_on_after_fail");
 187         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 188         byte &= ~0x40;
 189         if (!on) {
 190                 byte |= 0x40;
 191         }
 192         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 193         printk_info("set power %s after power fail\n", on?"on":"off");
 194 #endif
 195         /* Throttle the CPU speed down for testing */
 196         on = SLOW_CPU_OFF;
 197         get_option(&on, "slow_cpu");
 198         if(on) {
 199                 uint16_t pm10_bar;
 200                 uint32_t dword;
 201                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 202                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 203                 dword = inl(pm10_bar + 0x10);
 204                 on = 8-on;
 205                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 206                              (on*12)+(on>>1),(on&1)*5);
 207         }
 208
 209 #if 0
 210 // default is enabled
 211         /* Enable Port 92 fast reset */
 212         byte = pci_read_config8(dev, 0xe8);
 213         byte |= ~(1 << 3);
 214         pci_write_config8(dev, 0xe8, byte);
 215 #endif
 216
 217         /* Enable Error reporting */
 218         /* Set up sync flood detected */
 219         byte = pci_read_config8(dev, 0x47);
 220         byte |= (1 << 1);
 221         pci_write_config8(dev, 0x47, byte);
 222
 223         /* Set up NMI on errors */
 224         byte = inb(0x70); // RTC70
 225         byte_old = byte;
 226         nmi_option = NMI_OFF;
 227         get_option(&nmi_option, "nmi");
 228         if (nmi_option) {
 229                 byte &= ~(1 << 7); /* set NMI */
 230         } else {
 231                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 232         }
 233         if( byte != byte_old) {
 234                 outb(0x70, byte);
 235         }
 236
 237         /* Initialize the real time clock */
 238         rtc_init(0);
 239
 240         /* Initialize isa dma */
 241         isa_dma_init();
 242
 243         /* Initialize the High Precision Event Timers */
 244 //      enable_hpet(dev);
 245
 246 }
 247
 248 static void mcp55_lpc_read_resources(device_t dev)
 249 {
 250         struct resource *res;
 251
 252         /* Get the normal pci resources of this device */
 253         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 254
 255         /* Add an extra subtractive resource for both memory and I/O */
 256         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 257         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 258
 259         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 260         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 261
 262 }
 263
 264 /**
 265  * @brief Enable resources for children devices
 266  *
 267  * @param dev the device whos children's resources are to be enabled
 268  *
 269  * This function is call by the global enable_resources() indirectly via the
 270  * device_operation::enable_resources() method of devices.
 271  *
 272  * Indirect mutual recursion:
 273  *      enable_childrens_resources() -> enable_resources()
 274  *      enable_resources() -> device_operation::enable_resources()
 275  *      device_operation::enable_resources() -> enable_children_resources()
 276  */
 277 static void mcp55_lpc_enable_childrens_resources(device_t dev)
 278 {
 279         unsigned link;
 280         uint32_t reg, reg_var[4];
 281         int i;
 282         int var_num = 0;
 283
 284         reg = pci_read_config32(dev, 0xa0);
 285
 286         for (link = 0; link < dev->links; link++) {
 287                 device_t child;
 288                 for (child = dev->link[link].children; child; child = child->sibling) {
 289                         enable_resources(child);
 290                         if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 291                                 for(i=0;i<child->resources;i++) {
 292                                         struct resource *res;
 293                                         unsigned long base, end; // don't need long long
 294                                         res = &child->resource[i];
 295                                         if(!(res->flags & IORESOURCE_IO)) continue;
 296                                         base = res->base;
 297                                         end = resource_end(res);
 298                                         printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 299                                         switch(base) {
 300                                         case 0x3f8: // COM1
 301                                                 reg |= (1<<0);  break;
 302                                         case 0x2f8: // COM2
 303                                                 reg |= (1<<1);  break;
 304                                         case 0x378: // Parallal 1
 305                                                 reg |= (1<<24); break;
 306                                         case 0x3f0: // FD0
 307                                                 reg |= (1<<20); break;
 308                                         case 0x220:  // Aduio 0
 309                                                 reg |= (1<<8);  break;
 310                                         case 0x300:  // Midi 0
 311                                                 reg |= (1<<12); break;
 312                                         }
 313                                         if( (base == 0x290) || (base >= 0x400)) {
 314                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 315                                                 reg |= (1<<(28+var_num));
 316                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 317                                         }
 318                                 }
 319                         }
 320                 }
 321         }
 322         pci_write_config32(dev, 0xa0, reg);
 323         for(i=0;i<var_num;i++) {
 324                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 325         }
 326
 327
 328 }
 329
 330 static void mcp55_lpc_enable_resources(device_t dev)
 331 {
 332         pci_dev_enable_resources(dev);
 333         mcp55_lpc_enable_childrens_resources(dev);
 334 }
 335
 336 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 337 {
 338         pci_write_config32(dev, 0x40,
 339                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 340 }
 341
 342 static struct pci_operations lops_pci = {
 343         .set_subsystem  = lpci_set_subsystem,
 344 };
 345
 346 static struct device_operations lpc_ops  = {
 347         .read_resources = mcp55_lpc_read_resources,
 348         .set_resources  = pci_dev_set_resources,
 349         .enable_resources       = mcp55_lpc_enable_resources,
 350         .init           = lpc_init,
 351         .scan_bus       = scan_static_bus,
 352 //      .enable         = mcp55_enable,
 353         .ops_pci        = &lops_pci,
 354 };
 355 static const struct pci_driver lpc_driver __pci_driver = {
 356         .ops    = &lpc_ops,
 357         .vendor = PCI_VENDOR_ID_NVIDIA,
 358         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
 359 };
 360
 361 static const struct pci_driver lpc_driver_pro __pci_driver = {
 362         .ops    = &lpc_ops,
 363         .vendor = PCI_VENDOR_ID_NVIDIA,
 364         .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
 365 };
 366
 367 static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
 368         .ops    = &lpc_ops,
 369         .vendor = PCI_VENDOR_ID_NVIDIA,
 370         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
 371 };
 372 static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
 373         .ops    = &lpc_ops,
 374         .vendor = PCI_VENDOR_ID_NVIDIA,
 375         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
 376 };
 377 static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
 378         .ops    = &lpc_ops,
 379         .vendor = PCI_VENDOR_ID_NVIDIA,
 380         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
 381 };
 382 static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
 383         .ops    = &lpc_ops,
 384         .vendor = PCI_VENDOR_ID_NVIDIA,
 385         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
 386 };
 387 static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
 388         .ops    = &lpc_ops,
 389         .vendor = PCI_VENDOR_ID_NVIDIA,
 390         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
 391 };
 392
 393 static struct device_operations lpc_slave_ops  = {
 394         .read_resources = mcp55_lpc_read_resources,
 395         .set_resources  = pci_dev_set_resources,
 396         .enable_resources       = pci_dev_enable_resources,
 397         .init           = lpc_slave_init,
 398 //      .enable         = mcp55_enable,
 399         .ops_pci        = &lops_pci,
 400 };
 401
 402 static const struct pci_driver lpc_driver_slave __pci_driver = {
 403         .ops    = &lpc_slave_ops,
 404         .vendor = PCI_VENDOR_ID_NVIDIA,
 405         .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
 406 };