2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2004 Tyan Computer
7 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
8 * Copyright (C) 2006,2007 AMD
9 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <console/console.h>
27 #include <device/device.h>
28 #include <device/pci.h>
29 #include <device/pnp.h>
30 #include <device/pci_ids.h>
31 #include <device/pci_ops.h>
32 #include <pc80/mc146818rtc.h>
33 #include <pc80/isa-dma.h>
36 #include <arch/ioapic.h>
37 #include <cpu/x86/lapic.h>
44 #define PREVIOUS_POWER_STATE 0x7A
46 #define MAINBOARD_POWER_OFF 0
47 #define MAINBOARD_POWER_ON 1
48 #define SLOW_CPU_OFF 0
49 #define SLOW_CPU__ON 1
51 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
52 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
55 static void lpc_common_init(device_t dev, int master)
60 /* IO APIC initialization */
61 byte = pci_read_config8(dev, 0x74);
62 byte |= (1<<0); // enable APIC
63 pci_write_config8(dev, 0x74, byte);
64 ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
67 setup_ioapic(ioapic_base, 0);
69 clear_ioapic(ioapic_base);
72 static void lpc_slave_init(device_t dev)
74 lpc_common_init(dev, 0);
77 static void enable_hpet(struct device *dev)
79 unsigned long hpet_address;
81 pci_write_config32(dev,0x44, 0xfed00001);
82 hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
83 printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
86 static void lpc_init(device_t dev)
93 lpc_common_init(dev, 1);
96 /* posted memory write enable */
97 byte = pci_read_config8(dev, 0x46);
98 pci_write_config8(dev, 0x46, byte | (1<<0));
100 /* power after power fail */
103 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
104 get_option(&on, "power_on_after_fail");
105 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
110 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
111 printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
113 /* Throttle the CPU speed down for testing */
115 get_option(&on, "slow_cpu");
119 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
120 outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
121 dword = inl(pm10_bar + 0x10);
123 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
124 (on*12)+(on>>1),(on&1)*5);
128 // default is enabled
129 /* Enable Port 92 fast reset */
130 byte = pci_read_config8(dev, 0xe8);
132 pci_write_config8(dev, 0xe8, byte);
135 /* Enable Error reporting */
136 /* Set up sync flood detected */
137 byte = pci_read_config8(dev, 0x47);
139 pci_write_config8(dev, 0x47, byte);
141 /* Set up NMI on errors */
142 byte = inb(0x70); // RTC70
144 nmi_option = NMI_OFF;
145 get_option(&nmi_option, "nmi");
147 byte &= ~(1 << 7); /* set NMI */
149 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
151 if( byte != byte_old) {
155 /* Initialize the real time clock */
158 /* Initialize isa dma */
161 /* Initialize the High Precision Event Timers */
166 static void mcp55_lpc_read_resources(device_t dev)
168 struct resource *res;
170 /* Get the normal PCI resources of this device. */
171 /* We got one for APIC, or one more for TRAP. */
172 pci_dev_read_resources(dev);
174 /* Add an extra subtractive resource for both memory and I/O. */
175 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
178 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
179 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
181 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
182 res->base = 0xff800000;
183 res->size = 0x00800000; /* 8 MB for flash */
184 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
185 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
187 res = new_resource(dev, 3); /* IOAPIC */
188 res->base = IO_APIC_ADDR;
189 res->size = 0x00001000;
190 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
194 * @brief Enable resources for children devices
196 * @param dev the device whos children's resources are to be enabled
199 static void mcp55_lpc_enable_childrens_resources(device_t dev)
201 uint32_t reg, reg_var[4];
206 reg = pci_read_config32(dev, 0xa0);
208 for (link = dev->link_list; link; link = link->next) {
210 for (child = link->children; child; child = child->sibling) {
211 if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
212 struct resource *res;
213 for(res = child->resource_list; res; res = res->next) {
214 unsigned long base, end; // don't need long long
215 if(!(res->flags & IORESOURCE_IO)) continue;
217 end = resource_end(res);
218 printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
221 reg |= (1<<0); break;
223 reg |= (1<<1); break;
224 case 0x378: // Parallal 1
225 reg |= (1<<24); break;
227 reg |= (1<<20); break;
228 case 0x220: // Aduio 0
229 reg |= (1<<8); break;
230 case 0x300: // Midi 0
231 reg |= (1<<12); break;
233 if( (base == 0x290) || (base >= 0x400)) {
234 if(var_num>=4) continue; // only 4 var ; compact them ?
235 reg |= (1<<(28+var_num));
236 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
242 pci_write_config32(dev, 0xa0, reg);
243 for(i=0;i<var_num;i++) {
244 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
250 static void mcp55_lpc_enable_resources(device_t dev)
252 pci_dev_enable_resources(dev);
253 mcp55_lpc_enable_childrens_resources(dev);
256 static struct device_operations lpc_ops = {
257 .read_resources = mcp55_lpc_read_resources,
258 .set_resources = pci_dev_set_resources,
259 .enable_resources = mcp55_lpc_enable_resources,
261 .scan_bus = scan_static_bus,
262 // .enable = mcp55_enable,
263 .ops_pci = &mcp55_pci_ops,
265 static const struct pci_driver lpc_driver __pci_driver = {
267 .vendor = PCI_VENDOR_ID_NVIDIA,
268 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
271 static const struct pci_driver lpc_driver_pro __pci_driver = {
273 .vendor = PCI_VENDOR_ID_NVIDIA,
274 .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
277 static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
279 .vendor = PCI_VENDOR_ID_NVIDIA,
280 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
282 static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
284 .vendor = PCI_VENDOR_ID_NVIDIA,
285 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
287 static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
289 .vendor = PCI_VENDOR_ID_NVIDIA,
290 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
292 static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
294 .vendor = PCI_VENDOR_ID_NVIDIA,
295 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
297 static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
299 .vendor = PCI_VENDOR_ID_NVIDIA,
300 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
303 static struct device_operations lpc_slave_ops = {
304 .read_resources = mcp55_lpc_read_resources,
305 .set_resources = pci_dev_set_resources,
306 .enable_resources = pci_dev_enable_resources,
307 .init = lpc_slave_init,
308 // .enable = mcp55_enable,
309 .ops_pci = &mcp55_pci_ops,
312 static const struct pci_driver lpc_driver_slave __pci_driver = {
313 .ops = &lpc_slave_ops,
314 .vendor = PCI_VENDOR_ID_NVIDIA,
315 .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,