2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
24 static int set_ht_link_mcp55(uint8_t ht_c_num)
26 unsigned vendorid = 0x10de;
27 unsigned val = 0x01610109;
28 /* Nvidia mcp55 hardcode, hw can not set it automatically */
29 return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
32 static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
42 outl(0, index); //index
43 for(i = 0; i < max; i++) {
45 reg = register_values[i];
56 #define ANACTRL_IO_BASE 0x2800
57 #define ANACTRL_REG_POS 0x68
60 #define SYSCTRL_IO_BASE 0x2400
61 #define SYSCTRL_REG_POS 0x64
64 #define ACPICTRL_IO_BASE 0x2000
65 #define ACPICTRL_REG_POS 0x60
76 #ifndef MCP55_PCI_E_X_0
77 #define MCP55_PCI_E_X_0 4
79 #ifndef MCP55_PCI_E_X_1
80 #define MCP55_PCI_E_X_1 4
82 #ifndef MCP55_PCI_E_X_2
83 #define MCP55_PCI_E_X_2 4
85 #ifndef MCP55_PCI_E_X_3
86 #define MCP55_PCI_E_X_3 4
90 #define MCP55_USE_NIC 0
94 #define MCP55_USE_AZA 0
97 #define MCP55_CHIP_REV 3
99 static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
102 static const unsigned int ctrl_devport_conf[] = {
103 PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
104 PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
105 PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
109 for(j = 0; j < mcp55_num; j++ ) {
110 setup_resource_map_offset(ctrl_devport_conf,
111 ARRAY_SIZE(ctrl_devport_conf),
112 PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
116 static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
119 static const unsigned int ctrl_devport_conf_clear[] = {
120 PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
121 PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
122 PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
126 for(j = 0; j < mcp55_num; j++ ) {
127 setup_resource_map_offset(ctrl_devport_conf_clear,
128 ARRAY_SIZE(ctrl_devport_conf_clear),
129 PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
134 static void delayx(uint8_t value) {
137 for(i=0;i<0x8000;i++) {
143 static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
150 dev = PCI_DEV(busnx, devnx+1, 1);
151 dword = pci_read_config32(dev, 0xe4);
152 dword |= 0x3f0; // disable it at first
153 pci_write_config32(dev, 0xe4, dword);
156 tgio_ctrl = inl(anactrl_io_base + 0xcc);
157 tgio_ctrl &= ~(3<<9);
159 outl(tgio_ctrl, anactrl_io_base + 0xcc);
160 pll_ctrl = inl(anactrl_io_base + 0x30);
162 outl(pll_ctrl, anactrl_io_base + 0x30);
164 pll_ctrl = inl(anactrl_io_base + 0x30);
165 } while (!(pll_ctrl & 1));
167 tgio_ctrl = inl(anactrl_io_base + 0xcc);
168 tgio_ctrl &= ~((7<<4)|(1<<8));
169 tgio_ctrl |= (pci_e_x<<4)|(1<<8);
170 outl(tgio_ctrl, anactrl_io_base + 0xcc);
175 dword = pci_read_config32(dev, 0xe4);
176 dword &= ~(0x3f0); // enable
177 pci_write_config32(dev, 0xe4, dword);
179 // need to wait 100ms
183 static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
186 static const unsigned int ctrl_conf_1[] = {
187 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
188 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
189 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
190 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
192 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
193 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
194 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
195 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
196 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
197 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
198 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
199 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
200 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
201 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
202 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
203 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
204 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
205 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
206 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
207 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
208 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
210 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
211 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
212 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
213 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
214 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
215 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
216 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
218 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
219 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
220 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
222 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
223 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
224 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
226 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
227 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
228 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
230 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
231 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
232 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
235 static const unsigned int ctrl_conf_1_1[] = {
236 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
237 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
238 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
239 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
240 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
241 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
242 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
243 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
244 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
248 static const unsigned int ctrl_conf_mcp55_only[] = {
249 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
250 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
251 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
252 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
254 RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
255 RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
257 RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
259 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
260 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
261 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
262 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
263 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
264 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
265 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
267 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
268 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
269 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
270 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
271 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
272 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
273 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
274 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
276 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
278 #if MCP55_USE_AZA == 1
279 RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
281 // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
283 // play a while with GPIO in MCP55
284 #ifdef MCP55_MB_SETUP
288 #if MCP55_USE_AZA == 1
289 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
290 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
291 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
297 static const unsigned int ctrl_conf_master_only[] = {
299 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
301 //Master MCP55 ????YHLU
302 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
306 static const unsigned int ctrl_conf_2[] = {
307 /* I didn't put pcie related stuff here */
309 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
310 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
312 RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
314 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
317 #if MCP55_USE_NIC == 1
318 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
320 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
321 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
329 for(j=0; j<mcp55_num; j++) {
330 mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
332 setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
333 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
334 for(i=0; i<3; i++) { // three SATA
335 setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
336 PCI_DEV(busn[j], devn[j], i), io_base[j]);
339 setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
340 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
343 if( (busn[j] == 0) && (mcp55_num>1) ) {
344 setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
345 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
348 setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
349 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
354 for(j=0; j< mcp55_num; j++) {
355 // PCI-E (XSPLL) SS table 0x40, x044, 0x48
356 // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
357 // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
358 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
359 io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
360 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
361 io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
362 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
363 io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
369 #ifndef HT_CHAIN_NUM_MAX
371 #define HT_CHAIN_NUM_MAX 4
372 #define HT_CHAIN_BUSN_D 0x40
373 #define HT_CHAIN_IOBASE_D 0x4000
377 static int mcp55_early_setup_x(void)
379 /*find out how many mcp55 we have */
380 unsigned busn[HT_CHAIN_NUM_MAX];
381 unsigned devn[HT_CHAIN_NUM_MAX];
382 unsigned io_base[HT_CHAIN_NUM_MAX];
384 FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
385 Need to use same trick about pci1234 to verify node/link connection
387 unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 };
393 /* FIXME: multi pci segment handling */
395 /* Any system that only have IO55 without MCP55? */
396 for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
397 busnx = ht_c_index * HT_CHAIN_BUSN_D;
398 for(devnx=0;devnx<0x20;devnx++) {
401 dev = PCI_DEV(busnx, devnx, 0);
402 id = pci_read_config32(dev, PCI_VENDOR_ID);
403 if(id == 0x036910de) {
404 busn[mcp55_num] = busnx;
405 devn[mcp55_num] = devnx;
406 io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
408 if(mcp55_num == MCP55_NUM) goto out;
409 break; // only one MCP55 on one chain
415 print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n");
417 mcp55_early_set_port(mcp55_num, busn, devn, io_base);
418 mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
420 mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
422 // set_ht_link_mcp55(HT_CHAIN_NUM_MAX);