2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/pci_ops.h>
29 #ifndef CK804_SATA_RESET_FOR_ATAPI
30 #define CK804_SATA_RESET_FOR_ATAPI 0
33 #if CK804_SATA_RESET_FOR_ATAPI
34 static void sata_com_reset(struct device *dev, unsigned reset)
42 base = (u32 *) pci_read_config32(dev, 0x24);
44 printk(BIOS_DEBUG, "base = %08lx\n", base);
47 *(base + 4) = 0xffffffff;
48 *(base + 0x44) = 0xffffffff;
56 *(base + 0x48) = dword;
62 *(base + 0x48) = dword;
69 printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword);
74 if ((dword & 0x10000) != 0)
78 printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword);
81 dword = *(base + 0x40);
82 printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword);
86 dword = *(base + 0x44);
87 if ((dword & 0x10000) != 0)
91 printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword);
96 static void sata_init(struct device *dev)
99 struct southbridge_nvidia_ck804_config *conf;
101 conf = dev->chip_info;
103 dword = pci_read_config32(dev, 0x50);
104 /* Ensure prefetch is disabled. */
105 dword &= ~((1 << 15) | (1 << 13));
106 if (conf->sata1_enable) {
107 /* Enable secondary SATA interface. */
109 printk(BIOS_DEBUG, "SATA S \t");
111 if (conf->sata0_enable) {
112 /* Enable primary SATA interface. */
114 printk(BIOS_DEBUG, "SATA P \n");
129 /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
130 dword &= ~(0x1f << 24);
131 dword |= (0x15 << 24);
133 pci_write_config32(dev, 0x50, dword);
136 /* SLUMBER_DURING_D3 */
137 dword = pci_read_config32(dev, 0x7c);
139 pci_write_config32(dev, 0x7c, dword);
141 dword = pci_read_config32(dev, 0xd0);
142 dword &= ~(0xff << 24);
143 dword |= (0x68 << 24);
144 pci_write_config32(dev, 0xd0, dword);
146 dword = pci_read_config32(dev, 0xe0);
147 dword &= ~(0xff << 24);
148 dword |= (0x68 << 24);
149 pci_write_config32(dev, 0xe0, dword);
152 dword = pci_read_config32(dev, 0xf8);
154 pci_write_config32(dev, 0xf8, dword);
156 #if CK804_SATA_RESET_FOR_ATAPI
157 dword = pci_read_config32(dev, 0xac);
158 dword &= ~((1 << 13) | (1 << 14));
159 dword |= (1 << 13) | (0 << 14);
160 pci_write_config32(dev, 0xac, dword);
162 sata_com_reset(dev, 1); /* For discover some s-atapi device. */
166 static struct device_operations sata_ops = {
167 .read_resources = pci_dev_read_resources,
168 .set_resources = pci_dev_set_resources,
169 .enable_resources = pci_dev_enable_resources,
170 // .enable = ck804_enable,
173 .ops_pci = &ck804_pci_ops,
176 static const struct pci_driver sata0_driver __pci_driver = {
178 .vendor = PCI_VENDOR_ID_NVIDIA,
179 .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0,
182 static const struct pci_driver sata1_driver __pci_driver = {
184 .vendor = PCI_VENDOR_ID_NVIDIA,
185 .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1,