src/southbridge/nvidia/ck804/ck804_lpc.c

   1 /*
   2  * (C) 2003 Linux Networx, SuSE Linux AG
   3  * Copyright 2004 Tyan Computer
   4  *  by yhlu@tyan.com
   5  *  2006.1 yhlu add dest apicid for IRQ0
   6  */
   7 #include <console/console.h>
   8 #include <device/device.h>
   9 #include <device/pci.h>
  10 #include <device/pnp.h>
  11 #include <device/pci_ids.h>
  12 #include <device/pci_ops.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <pc80/isa-dma.h>
  15 #include <bitops.h>
  16 #include <arch/io.h>
  17 #include <cpu/x86/lapic.h>
  18 #include "ck804.h"
  19
  20 #define CK804_CHIP_REV 2
  21
  22 #define NMI_OFF 0
  23
  24 struct ioapicreg {
  25         unsigned int reg;
  26         unsigned int value_low, value_high;
  27 };
  28
  29 static struct ioapicreg ioapicregvalues[] = {
  30 #define ALL             (0xff << 24)
  31 #define NONE            (0)
  32 #define DISABLED        (1 << 16)
  33 #define ENABLED         (0 << 16)
  34 #define TRIGGER_EDGE    (0 << 15)
  35 #define TRIGGER_LEVEL   (1 << 15)
  36 #define POLARITY_HIGH   (0 << 13)
  37 #define POLARITY_LOW    (1 << 13)
  38 #define PHYSICAL_DEST   (0 << 11)
  39 #define LOGICAL_DEST    (1 << 11)
  40 #define ExtINT          (7 << 8)
  41 #define NMI             (4 << 8)
  42 #define SMI             (2 << 8)
  43 #define INT             (1 << 8)
  44         /* IO-APIC virtual wire mode configuration */
  45         /* mask, trigger, polarity, destination, delivery, vector */
  46         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  47         {   1, DISABLED, NONE},
  48         {   2, DISABLED, NONE},
  49         {   3, DISABLED, NONE},
  50         {   4, DISABLED, NONE},
  51         {   5, DISABLED, NONE},
  52         {   6, DISABLED, NONE},
  53         {   7, DISABLED, NONE},
  54         {   8, DISABLED, NONE},
  55         {   9, DISABLED, NONE},
  56         {  10, DISABLED, NONE},
  57         {  11, DISABLED, NONE},
  58         {  12, DISABLED, NONE},
  59         {  13, DISABLED, NONE},
  60         {  14, DISABLED, NONE},
  61         {  15, DISABLED, NONE},
  62         {  16, DISABLED, NONE},
  63         {  17, DISABLED, NONE},
  64         {  18, DISABLED, NONE},
  65         {  19, DISABLED, NONE},
  66         {  20, DISABLED, NONE},
  67         {  21, DISABLED, NONE},
  68         {  22, DISABLED, NONE},
  69         {  23, DISABLED, NONE},
  70         /* Be careful and don't write past the end... */
  71 };
  72
  73 static void setup_ioapic(unsigned long ioapic_base)
  74 {
  75         int i;
  76         unsigned long value_low, value_high;
  77 //      unsigned long ioapic_base = 0xfec00000;
  78         volatile unsigned long *l;
  79         struct ioapicreg *a = ioapicregvalues;
  80
  81         ioapicregvalues[0].value_high = lapicid()<<(56-32);
  82
  83         l = (unsigned long *) ioapic_base;
  84
  85         for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
  86              i++, a++) {
  87                 l[0] = (a->reg * 2) + 0x10;
  88                 l[4] = a->value_low;
  89                 value_low = l[4];
  90                 l[0] = (a->reg *2) + 0x11;
  91                 l[4] = a->value_high;
  92                 value_high = l[4];
  93                 if ((i==0) && (value_low == 0xffffffff)) {
  94                         printk_warning("IO APIC not responding.\n");
  95                         return;
  96                 }
  97                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
  98                             a->reg, a->value_low, a->value_high);
  99         }
 100 }
 101
 102 // 0x7a or e3
 103 #define PREVIOUS_POWER_STATE 0x7A
 104
 105 #define MAINBOARD_POWER_OFF 0
 106 #define MAINBOARD_POWER_ON 1
 107 #define SLOW_CPU_OFF 0
 108 #define SLOW_CPU__ON 1
 109
 110 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 111 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 112 #endif
 113
 114 static void lpc_common_init(device_t dev)
 115 {
 116         uint8_t byte;
 117         uint32_t dword;
 118
 119         /* IO APIC initialization */
 120         byte = pci_read_config8(dev, 0x74);
 121         byte |= (1<<0); // enable APIC
 122         pci_write_config8(dev, 0x74, byte);
 123         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 124
 125         setup_ioapic(dword);
 126
 127 #if 1
 128         dword = pci_read_config32(dev, 0xe4);
 129         dword |= (1<<23);
 130         pci_write_config32(dev, 0xe4, dword);
 131 #endif
 132
 133 }
 134
 135 static void lpc_slave_init(device_t dev)
 136 {
 137         lpc_common_init(dev);
 138 }
 139
 140 static void rom_dummy_write(device_t dev){
 141         uint8_t old, new;
 142         uint8_t *p;
 143
 144         old = pci_read_config8(dev, 0x88);
 145         new = old | 0xc0;
 146         if (new != old) {
 147                 pci_write_config8(dev, 0x88, new);
 148         }
 149         //  enable write
 150         old = pci_read_config8(dev, 0x6d);
 151         new = old | 0x01;
 152         if (new != old) {
 153                 pci_write_config8(dev, 0x6d, new);
 154         }
 155
 156         /* dummy write */
 157         p = (uint8_t *)0xffffffe0;
 158         old = 0;
 159         *p = old;
 160         old = *p;
 161
 162         //  disable write
 163         old = pci_read_config8(dev, 0x6d);
 164         new = old & 0xfe;
 165         if (new != old) {
 166                 pci_write_config8(dev, 0x6d, new);
 167
 168         }
 169
 170 }
 171 #if 0
 172 static void enable_hpet(struct device *dev)
 173 {
 174         unsigned long hpet_address;
 175
 176         pci_write_config32(dev,0x44, 0xfed00001);
 177         hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 178         printk_debug("enabling HPET @0x%x\n", hpet_address);
 179 }
 180 #endif
 181
 182 static void lpc_init(device_t dev)
 183 {
 184         uint8_t byte;
 185         uint8_t byte_old;
 186         int on;
 187         int nmi_option;
 188
 189         lpc_common_init(dev);
 190
 191 #if CK804_CHIP_REV==1
 192         if(dev->bus->secondary!=1) return;
 193 #endif
 194
 195 #if 0
 196         /* posted memory write enable */
 197         byte = pci_read_config8(dev, 0x46);
 198         pci_write_config8(dev, 0x46, byte | (1<<0));
 199
 200 #endif
 201         /* power after power fail */
 202
 203         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 204         get_option(&on, "power_on_after_fail");
 205         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 206         byte &= ~0x40;
 207         if (!on) {
 208                 byte |= 0x40;
 209         }
 210         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 211         printk_info("set power %s after power fail\n", on?"on":"off");
 212
 213         /* Throttle the CPU speed down for testing */
 214         on = SLOW_CPU_OFF;
 215         get_option(&on, "slow_cpu");
 216         if(on) {
 217                 uint16_t pm10_bar;
 218                 uint32_t dword;
 219                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 220                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 221                 dword = inl(pm10_bar + 0x10);
 222                 on = 8-on;
 223                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 224                                 (on*12)+(on>>1),(on&1)*5);
 225         }
 226
 227 #if 0
 228 // default is enabled
 229         /* Enable Port 92 fast reset */
 230         byte = pci_read_config8(dev, 0xe8);
 231         byte |= ~(1 << 3);
 232         pci_write_config8(dev, 0xe8, byte);
 233 #endif
 234
 235         /* Enable Error reporting */
 236         /* Set up sync flood detected */
 237         byte = pci_read_config8(dev, 0x47);
 238         byte |= (1 << 1);
 239         pci_write_config8(dev, 0x47, byte);
 240
 241         /* Set up NMI on errors */
 242         byte = inb(0x70); // RTC70
 243         byte_old = byte;
 244         nmi_option = NMI_OFF;
 245         get_option(&nmi_option, "nmi");
 246         if (nmi_option) {
 247                 byte &= ~(1 << 7); /* set NMI */
 248         } else {
 249                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 250         }
 251         if( byte != byte_old) {
 252                 outb(0x70, byte);
 253         }
 254
 255         /* Initialize the real time clock */
 256         rtc_init(0);
 257
 258         /* Initialize isa dma */
 259         isa_dma_init();
 260
 261         /* Initialize the High Precision Event Timers */
 262 //        enable_hpet(dev);
 263
 264         rom_dummy_write(dev);
 265
 266 }
 267
 268 static void ck804_lpc_read_resources(device_t dev)
 269 {
 270         struct resource *res;
 271         unsigned long index;
 272
 273         /* Get the normal pci resources of this device */
 274         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 275
 276         /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */
 277         for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
 278                 pci_get_resource(dev, index);
 279         }
 280         compact_resources(dev);
 281
 282         /* Add an extra subtractive resource for both memory and I/O */
 283         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 284         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 285
 286         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 287         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 288
 289 }
 290
 291 /**
 292  * @brief Enable resources for children devices
 293  *
 294  * @param dev the device whos children's resources are to be enabled
 295  *
 296  * This function is call by the global enable_resources() indirectly via the
 297  * device_operation::enable_resources() method of devices.
 298  *
 299  * Indirect mutual recursion:
 300  *      enable_childrens_resources() -> enable_resources()
 301  *      enable_resources() -> device_operation::enable_resources()
 302  *      device_operation::enable_resources() -> enable_children_resources()
 303  */
 304 static void ck804_lpc_enable_childrens_resources(device_t dev)
 305 {
 306         unsigned link;
 307         uint32_t reg, reg_var[4];
 308         int i;
 309         int var_num = 0;
 310
 311         reg = pci_read_config32(dev, 0xa0);
 312
 313         for (link = 0; link < dev->links; link++) {
 314                 device_t child;
 315                 for (child = dev->link[link].children; child; child = child->sibling) {
 316                         enable_resources(child);
 317                         if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 318                                 for(i=0;i<child->resources;i++) {
 319                                         struct resource *res;
 320                                         unsigned long base, end; // don't need long long
 321                                         res = &child->resource[i];
 322                                         if(!(res->flags & IORESOURCE_IO)) continue;
 323                                         base = res->base;
 324                                         end = resource_end(res);
 325                                         printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
 326                                         switch(base) {
 327                                         case 0x3f8: // COM1
 328                                                 reg |= (1<<0);  break;
 329                                         case 0x2f8: // COM2
 330                                                 reg |= (1<<1);  break;
 331                                         case 0x378: // Parallal 1
 332                                                 reg |= (1<<24); break;
 333                                         case 0x3f0: // FD0
 334                                                 reg |= (1<<20); break;
 335                                         case 0x220:  // Aduio 0
 336                                                 reg |= (1<<8);  break;
 337                                         case 0x300:  // Midi 0
 338                                                 reg |= (1<<12); break;
 339                                         }
 340                                         if( base == 0x290 || base >= 0x400) {
 341                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 342                                                 reg |= (1<<(28+var_num));
 343                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 344                                         }
 345                                 }
 346                         }
 347                 }
 348         }
 349         pci_write_config32(dev, 0xa0, reg);
 350         for(i=0;i<var_num;i++) {
 351                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 352         }
 353
 354
 355 }
 356
 357 static void ck804_lpc_enable_resources(device_t dev)
 358 {
 359         pci_dev_enable_resources(dev);
 360         ck804_lpc_enable_childrens_resources(dev);
 361 }
 362
 363 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 364 {
 365         pci_write_config32(dev, 0x40,
 366                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 367 }
 368
 369 static struct pci_operations lops_pci = {
 370         .set_subsystem = lpci_set_subsystem,
 371 };
 372
 373 static struct device_operations lpc_ops  = {
 374         .read_resources   = ck804_lpc_read_resources,
 375         .set_resources    = pci_dev_set_resources,
 376         .enable_resources = ck804_lpc_enable_resources,
 377         .init             = lpc_init,
 378         .scan_bus         = scan_static_bus,
 379 //      .enable           = ck804_enable,
 380         .ops_pci          = &lops_pci,
 381 };
 382 static struct pci_driver lpc_driver __pci_driver = {
 383         .ops    = &lpc_ops,
 384         .vendor = PCI_VENDOR_ID_NVIDIA,
 385         .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
 386 };
 387
 388 static struct pci_driver lpc_driver_pro __pci_driver = {
 389         .ops    = &lpc_ops,
 390         .vendor = PCI_VENDOR_ID_NVIDIA,
 391         .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
 392 };
 393
 394 #if CK804_CHIP_REV == 1
 395 static struct pci_driver lpc_driver_slave __pci_driver = {
 396         .ops    = &lpc_ops,
 397         .vendor = PCI_VENDOR_ID_NVIDIA,
 398         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 399 };
 400 #else
 401 static struct device_operations lpc_slave_ops  = {
 402         .read_resources   = ck804_lpc_read_resources,
 403         .set_resources    = pci_dev_set_resources,
 404         .enable_resources = pci_dev_enable_resources,
 405         .init             = lpc_slave_init,
 406 //        .enable           = ck804_enable,
 407         .ops_pci          = &lops_pci,
 408 };
 409
 410 static struct pci_driver lpc_driver_slave __pci_driver = {
 411         .ops    = &lpc_slave_ops,
 412         .vendor = PCI_VENDOR_ID_NVIDIA,
 413         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 414 };
 415 #endif