src/southbridge/nvidia/ck804/ck804_early_setup_car.c

   1 /*
   2  * Copyright 2004 Tyan Computer
   3  *  by yhlu@tyan.com
   4  * 2005.12 yhlu make it for car so it could support more ck804s
   5  */
   6 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
   7 {
   8         uint32_t dword, dword_old;
   9         uint8_t link_type;
  10
  11         /* This works on an Athlon64 because unimplemented links return 0 */
  12         dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
  13         link_type = dword & 0xff;
  14
  15         dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) );
  16
  17         if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
  18                 dword = val;
  19         }
  20
  21         if (dword != dword_old) {
  22                 pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword);
  23                 return 1;
  24         }
  25
  26         return 0;
  27 }
  28 static int set_ht_link_ck804(uint8_t ht_c_num)
  29 {
  30         int reset_needed;
  31         uint8_t i;
  32
  33         reset_needed = 0;
  34
  35         for (i = 0; i < ht_c_num; i++) {
  36                 uint32_t reg;
  37                 uint8_t nodeid, linkn;
  38                 uint8_t busn;
  39                 unsigned val;
  40
  41                 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
  42                 if((reg & 3) != 3) continue;
  43
  44                 nodeid = ((reg & 0xf0)>>4);
  45                 linkn = ((reg & 0xf00)>>8);
  46                 busn = (reg & 0xff0000)>>16;
  47
  48                 reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID);
  49                 if ( (reg & 0xffff) == 0x10de ) {
  50                         val = 0x01610169;
  51                         reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
  52                 }
  53         }
  54
  55         return reset_needed;
  56 }
  57
  58
  59 static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
  60 {
  61         int i;
  62
  63         unsigned val;
  64         val = inl(control);
  65         val &= 0xfffffffe;
  66         outl(val, control);
  67
  68         outl(0, index);
  69
  70         for(i = 0; i < max; i++) {
  71                 unsigned long reg;
  72
  73                 reg = register_values[i];
  74                 outl(reg, where);
  75         }
  76         val = inl(control);
  77         val |= 1;
  78         outl(val, control);
  79
  80 }
  81
  82 #define ANACTRL_IO_BASE 0x3000
  83 #define ANACTRL_REG_POS 0x68
  84
  85
  86 #define SYSCTRL_IO_BASE 0x2000
  87 #define SYSCTRL_REG_POS 0x64
  88
  89 /*
  90         16 1 1 2 :0
  91          8 8 2 2 :1
  92          8 8 4   :2
  93          8 4 4 4 :3
  94         16 4     :4
  95 */
  96
  97 #ifndef CK804_PCI_E_X
  98         #define CK804_PCI_E_X 4
  99 #endif
 100
 101         /* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
 102         #define CK804B_ANACTRL_IO_BASE 0x3000
 103         #define CK804B_SYSCTRL_IO_BASE 0x2000
 104
 105         #ifdef CK804B_BUSN
 106                 #undef CK804B_BUSN
 107         #endif
 108         #define CK804B_BUSN 0x0
 109
 110         #ifndef CK804B_PCI_E_X
 111                 #define CK804B_PCI_E_X 4
 112         #endif
 113
 114 #ifndef CK804_USE_NIC
 115         #define CK804_USE_NIC 0
 116 #endif
 117
 118 #ifndef CK804_USE_ACI
 119         #define CK804_USE_ACI 0
 120 #endif
 121
 122 #define CK804_CHIP_REV 3
 123
 124 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 125         #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 126 #else
 127         #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 128 #endif
 129
 130 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 131         #define CK804B_DEVN_BASE 1
 132 #else
 133         #define CK804B_DEVN_BASE CK804_DEVN_BASE
 134 #endif
 135
 136 static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
 137 {
 138
 139         static const unsigned int ctrl_devport_conf[] = {
 140                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
 141                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
 142         };
 143
 144         static const unsigned int ctrl_devport_conf_b[] = {
 145                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
 146                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
 147         };
 148
 149         int j;
 150         for(j = 0; j < ck804_num; j++ ) {
 151                 if(busn[j]==0) { //sb chain
 152                         setup_resource_map_offset(ctrl_devport_conf,
 153                                  sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
 154                                 PCI_DEV(busn[j], 0, 0) , io_base[j]);
 155                         continue;
 156                 }
 157                 setup_resource_map_offset(ctrl_devport_conf_b,
 158                         sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
 159                         PCI_DEV(busn[j], 0, 0) , io_base[j]);
 160         }
 161 }
 162
 163 static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
 164 {
 165
 166         static const unsigned int ctrl_devport_conf_clear[] = {
 167                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 168                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 169         };
 170
 171         static const unsigned int ctrl_devport_conf_clear_b[] = {
 172                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 173                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 174         };
 175
 176         int j;
 177         for(j = 0; j < ck804_num; j++ ) {
 178                 if(busn[j]==0) { //sb chain
 179                         setup_resource_map_offset(ctrl_devport_conf_clear,
 180                                 sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
 181                                 PCI_DEV(busn[j], 0, 0) , io_base[j]);
 182                         continue;
 183                 }
 184                 setup_resource_map_offset(ctrl_devport_conf_clear_b,
 185                         sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
 186                         PCI_DEV(busn[j], 0, 0) , io_base[j]);
 187         }
 188
 189
 190 }
 191
 192
 193 static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
 194 {
 195
 196         static const unsigned int ctrl_conf_master[] = {
 197
 198         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
 199         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
 200         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
 201         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
 202
 203
 204         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
 205         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
 206         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
 207         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
 208         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
 209         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
 210         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
 211         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
 212
 213
 214         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
 215         RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
 216
 217
 218         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
 219         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
 220         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
 221
 222
 223 #ifdef CK804_MB_SETUP
 224         CK804_MB_SETUP
 225 #endif
 226
 227
 228 #if CK804_NUM > 1
 229         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
 230         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
 231
 232 #endif
 233
 234 #if CK804_NUM == 1
 235         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
 236         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
 237
 238 #endif
 239
 240         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 241         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 242         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 243         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 244         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 245         RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 246
 247         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
 248         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
 249         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
 250
 251
 252         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 253
 254     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
 255     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
 256     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
 257     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
 258     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
 259     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
 260     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
 261     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 262     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
 263     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
 264
 265
 266                 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
 267
 268 //PANTA         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
 269
 270                 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
 271
 272                 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
 273
 274
 275 //SYSCTRL
 276
 277
 278                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
 279                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
 280 #if CK804_USE_NIC == 1
 281                 RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
 282                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 283                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 284                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
 285                 RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
 286 #endif
 287
 288 #if CK804_USE_ACI == 1
 289                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
 290                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
 291 #endif
 292
 293 #if CK804_NUM > 1
 294                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
 295 #endif
 296
 297
 298         };
 299
 300
 301
 302
 303         static const unsigned int ctrl_conf_slave[] = {
 304
 305
 306         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
 307         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
 308         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
 309
 310
 311         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
 312         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
 313         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
 314         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
 315         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
 316         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
 317         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
 318         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
 319
 320
 321         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
 322         RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
 323
 324         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
 325         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
 326         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
 327
 328         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
 329         RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
 330         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
 331
 332         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 333         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 334         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 335         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 336         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 337         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 338
 339         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 340
 341     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
 342     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
 343     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
 344     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
 345     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
 346     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
 347     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
 348     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 349     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
 350     RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
 351
 352
 353                 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
 354
 355 //PANTA         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
 356
 357                 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
 358
 359                 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
 360
 361         #if CK804_USE_NIC == 1
 362                 RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
 363                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 364                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 365                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
 366                 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
 367         #endif
 368
 369         };
 370
 371         int j;
 372
 373         for(j=0; j<ck804_num; j++) {
 374                 if(busn[j] == 0) {
 375                         setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
 376                                 PCI_DEV(busn[0],0,0), io_base[0]);
 377                         continue;
 378                 }
 379
 380
 381                 setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
 382                         PCI_DEV(busn[j],0,0), io_base[j]);
 383         }
 384
 385         for(j=0; j< ck804_num; j++) {
 386                 // PCI-E (XSPLL) SS table 0x40, x044, 0x48
 387                 // SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
 388                 // CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
 389                 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
 390                         io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
 391                 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
 392                         io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
 393 //PANTA                setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
 394 //                        io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
 395         }
 396
 397
 398 }
 399
 400 static int ck804_early_setup_x(void)
 401 {
 402         unsigned busn[4];
 403         unsigned io_base[4];
 404         int ck804_num = 0;
 405         int i;
 406
 407         for(i=0;i<4;i++) {
 408                 uint32_t id;
 409                 device_t dev;
 410                 if(i == 0) { // SB chain
 411                         dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
 412                 }
 413                 else {
 414                         dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
 415                 }
 416                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 417                 if(id == 0x005e10de) {
 418                         busn[ck804_num] = i * 0x40;
 419                         io_base[ck804_num] = i * 0x4000;
 420                         ck804_num++;
 421                 }
 422         }
 423
 424         ck804_early_set_port(ck804_num, busn, io_base);
 425         ck804_early_setup(ck804_num, busn, io_base);
 426         ck804_early_clear_port(ck804_num, busn, io_base);
 427         return set_ht_link_ck804(4);
 428 }