src/southbridge/nvidia/ck804/ck804_early_setup_car.c

   1 /*
   2  * Copyright 2004 Tyan Computer
   3  *  by yhlu@tyan.com
   4  * 2005.12 yhlu make it for car so it could support more ck804s
   5  */
   6
   7 static int set_ht_link_ck804(uint8_t ht_c_num)
   8 {
   9         unsigned vendorid = 0x10de;
  10         unsigned val = 0x01610169;
  11         return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
  12 }
  13
  14 static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
  15 {
  16         int i;
  17
  18         unsigned val;
  19         val = inl(control);
  20         val &= 0xfffffffe;
  21         outl(val, control);
  22
  23         outl(0, index);
  24
  25         for(i = 0; i < max; i++) {
  26                 unsigned long reg;
  27
  28                 reg = register_values[i];
  29                 outl(reg, where);
  30         }
  31         val = inl(control);
  32         val |= 1;
  33         outl(val, control);
  34
  35 }
  36
  37 #define ANACTRL_IO_BASE 0x3000
  38 #define ANACTRL_REG_POS 0x68
  39
  40
  41 #define SYSCTRL_IO_BASE 0x2000
  42 #define SYSCTRL_REG_POS 0x64
  43
  44 /*
  45         16 1 1 2 :0
  46          8 8 2 2 :1
  47          8 8 4   :2
  48          8 4 4 4 :3
  49         16 4     :4
  50 */
  51
  52 #ifndef CK804_PCI_E_X
  53         #define CK804_PCI_E_X 4
  54 #endif
  55
  56         /* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
  57         #define CK804B_ANACTRL_IO_BASE 0x3000
  58         #define CK804B_SYSCTRL_IO_BASE 0x2000
  59
  60         #ifdef CK804B_BUSN
  61                 #undef CK804B_BUSN
  62         #endif
  63         #define CK804B_BUSN 0x0
  64
  65         #ifndef CK804B_PCI_E_X
  66                 #define CK804B_PCI_E_X 4
  67         #endif
  68
  69 #ifndef CK804_USE_NIC
  70         #define CK804_USE_NIC 0
  71 #endif
  72
  73 #ifndef CK804_USE_ACI
  74         #define CK804_USE_ACI 0
  75 #endif
  76
  77 #define CK804_CHIP_REV 3
  78
  79 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  80         #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
  81 #else
  82         #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
  83 #endif
  84
  85 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
  86         #define CK804B_DEVN_BASE 1
  87 #else
  88         #define CK804B_DEVN_BASE CK804_DEVN_BASE
  89 #endif
  90
  91 static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
  92 {
  93
  94         static const unsigned int ctrl_devport_conf[] = {
  95                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
  96                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
  97         };
  98
  99         static const unsigned int ctrl_devport_conf_b[] = {
 100                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
 101                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
 102         };
 103
 104         int j;
 105         for(j = 0; j < ck804_num; j++ ) {
 106                 if(busn[j]==0) { //sb chain
 107                         setup_resource_map_offset(ctrl_devport_conf,
 108                                  sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
 109                                 PCI_DEV(busn[j], 0, 0) , io_base[j]);
 110                         continue;
 111                 }
 112                 setup_resource_map_offset(ctrl_devport_conf_b,
 113                         sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
 114                         PCI_DEV(busn[j], 0, 0) , io_base[j]);
 115         }
 116 }
 117
 118 static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
 119 {
 120
 121         static const unsigned int ctrl_devport_conf_clear[] = {
 122                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 123                 PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 124         };
 125
 126         static const unsigned int ctrl_devport_conf_clear_b[] = {
 127                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 128                 PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 129         };
 130
 131         int j;
 132         for(j = 0; j < ck804_num; j++ ) {
 133                 if(busn[j]==0) { //sb chain
 134                         setup_resource_map_offset(ctrl_devport_conf_clear,
 135                                 sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
 136                                 PCI_DEV(busn[j], 0, 0) , io_base[j]);
 137                         continue;
 138                 }
 139                 setup_resource_map_offset(ctrl_devport_conf_clear_b,
 140                         sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
 141                         PCI_DEV(busn[j], 0, 0) , io_base[j]);
 142         }
 143
 144
 145 }
 146
 147
 148 static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
 149 {
 150
 151         static const unsigned int ctrl_conf_master[] = {
 152
 153         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
 154         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
 155         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
 156         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
 157
 158
 159         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
 160         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
 161         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
 162         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
 163         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
 164         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
 165         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
 166         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
 167
 168
 169         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
 170         RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
 171
 172
 173         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
 174         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
 175         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
 176
 177
 178 #ifdef CK804_MB_SETUP
 179         CK804_MB_SETUP
 180 #endif
 181
 182
 183 #if CK804_NUM > 1
 184         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
 185         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
 186
 187 #endif
 188
 189 #if CK804_NUM == 1
 190         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
 191         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
 192
 193 #endif
 194
 195         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 196         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 197         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 198         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 199         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 200         RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 201
 202         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
 203         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
 204         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
 205
 206
 207         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 208
 209         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
 210         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
 211         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
 212         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
 213         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
 214         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
 215         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
 216         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 217         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
 218         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
 219
 220
 221         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
 222
 223 //PANTA         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
 224
 225         RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
 226
 227         RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
 228
 229
 230 //SYSCTRL
 231
 232
 233         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
 234         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
 235 #if CK804_USE_NIC == 1
 236         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
 237         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 238         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 239         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
 240         RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
 241 #endif
 242
 243 #if CK804_USE_ACI == 1
 244         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
 245         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
 246 #endif
 247
 248 #if CK804_NUM > 1
 249         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
 250 #endif
 251
 252
 253         };
 254
 255
 256
 257
 258         static const unsigned int ctrl_conf_slave[] = {
 259
 260
 261         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
 262         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
 263         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
 264
 265
 266         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
 267         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
 268         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
 269         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
 270         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
 271         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
 272         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
 273         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
 274
 275
 276         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
 277         RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
 278
 279         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
 280         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
 281         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
 282
 283         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
 284         RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
 285         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
 286
 287         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 288         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 289         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 290         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 291         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 292         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 293
 294         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 295
 296         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
 297         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
 298         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
 299         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
 300         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
 301         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
 302         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
 303         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 304         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
 305         RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
 306
 307
 308         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
 309
 310 //PANTA         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
 311
 312         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
 313
 314         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
 315
 316         #if CK804_USE_NIC == 1
 317                 RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
 318                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 319                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
 320                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
 321                 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
 322         #endif
 323
 324         };
 325
 326         int j;
 327
 328         for(j=0; j<ck804_num; j++) {
 329                 if(busn[j] == 0) {
 330                         setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
 331                                 PCI_DEV(busn[0],0,0), io_base[0]);
 332                         continue;
 333                 }
 334
 335
 336                 setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
 337                         PCI_DEV(busn[j],0,0), io_base[j]);
 338         }
 339
 340         for(j=0; j< ck804_num; j++) {
 341                 // PCI-E (XSPLL) SS table 0x40, x044, 0x48
 342                 // SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
 343                 // CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
 344                 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
 345                         io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
 346                 setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
 347                         io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
 348 //PANTA         setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
 349 //                      io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
 350         }
 351
 352
 353 }
 354
 355 static int ck804_early_setup_x(void)
 356 {
 357         unsigned busn[4];
 358         unsigned io_base[4];
 359         int ck804_num = 0;
 360         int i;
 361
 362         for(i=0;i<4;i++) {
 363                 uint32_t id;
 364                 device_t dev;
 365                 if(i == 0) { // SB chain
 366                         dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
 367                 }
 368                 else {
 369                         dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
 370                 }
 371                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 372                 if(id == 0x005e10de) {
 373                         busn[ck804_num] = i * 0x40;
 374                         io_base[ck804_num] = i * 0x4000;
 375                         ck804_num++;
 376                 }
 377         }
 378
 379         ck804_early_set_port(ck804_num, busn, io_base);
 380         ck804_early_setup(ck804_num, busn, io_base);
 381         ck804_early_clear_port(ck804_num, busn, io_base);
 382         return set_ht_link_ck804(4);
 383 }
 384
 385 static void hard_reset(void)
 386 {
 387         set_bios_reset();
 388
 389         /* full reset */
 390         outb(0x0a, 0x0cf9);
 391         outb(0x0e, 0x0cf9);
 392 }
 393
 394 static void soft_reset(void)
 395 {
 396         set_bios_reset();
 397
 398         /* link reset */
 399         outb(0x02, 0x0cf9);
 400         outb(0x06, 0x0cf9);
 401 }
 402