src/southbridge/intel/sch/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2009-2010 iWave Systems
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #include <console/console.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <arch/io.h>
  27
  28 #include "chip.h"
  29
  30
  31 /*SCH LPC defines*/
  32 #define SCH_ACPI_CTL            0x58
  33 #define SCH_SIRQ_CTL            0x68
  34 #define PIRQA_ROUT              0x60
  35 #define PIRQB_ROUT              0x61
  36 #define PIRQC_ROUT              0x62
  37 #define PIRQD_ROUT              0x63
  38 #define PIRQE_ROUT              0x64
  39 #define PIRQF_ROUT              0x65
  40 #define PIRQG_ROUT              0x66
  41 #define PIRQH_ROUT              0x67
  42
  43 typedef struct southbridge_intel_sch_config config_t;
  44
  45 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  46  * 0x00 - 0000 = Reserved
  47  * 0x01 - 0001 = Reserved
  48  * 0x02 - 0010 = Reserved
  49  * 0x03 - 0011 = IRQ3
  50  * 0x04 - 0100 = IRQ4
  51  * 0x05 - 0101 = IRQ5
  52  * 0x06 - 0110 = IRQ6
  53  * 0x07 - 0111 = IRQ7
  54  * 0x08 - 1000 = Reserved
  55  * 0x09 - 1001 = IRQ9
  56  * 0x0A - 1010 = IRQ10
  57  * 0x0B - 1011 = IRQ11
  58  * 0x0C - 1100 = IRQ12
  59  * 0x0D - 1101 = Reserved
  60  * 0x0E - 1110 = IRQ14
  61  * 0x0F - 1111 = IRQ15
  62  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  63  * 0x80 - The PIRQ is not routed.
  64  */
  65
  66 #define PIRQA 0x03
  67 #define PIRQB 0x05
  68 #define PIRQC 0x06
  69 #define PIRQD 0x07
  70 #define PIRQE 0x09
  71 #define PIRQF 0x0A
  72 #define PIRQG 0x0B
  73 #define PIRQH 0x0C
  74 static void sch_pirq_init(device_t dev)
  75 {
  76         device_t irq_dev;
  77         /* Get the chip configuration */
  78         config_t *config = dev->chip_info;
  79
  80         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
  81         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
  82         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
  83         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
  84
  85         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
  86         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
  87         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
  88         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
  89
  90         /* Eric Biederman once said we should let the OS do this.
  91          * I am not so sure anymore he was right.
  92          */
  93
  94         for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next)
  95          {
  96                 u8 int_pin=0, int_line=0;
  97
  98                 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
  99                         continue;
 100
 101                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 102
 103                 switch (int_pin)
 104                 {
 105                         case 1: /* INTA# */ int_line = config->pirqa_routing; break;
 106                         case 2: /* INTB# */ int_line = config->pirqb_routing; break;
 107                         case 3: /* INTC# */ int_line = config->pirqc_routing; break;
 108                         case 4: /* INTD# */ int_line = config->pirqd_routing; break;
 109                 }
 110
 111                 if (!int_line)
 112                         continue;
 113
 114                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 115         }
 116 }
 117 static void sch_fixups(struct device *dev)
 118 {
 119        u32 rcba_base;
 120         /* This needs to happen after PCI enumeration
 121         RCBA32(0x1d40) |= 1;*/
 122         rcba_base = pci_read_config32(dev, 0xF0);
 123         /*Remove the enable bit*/
 124         rcba_base = rcba_base >> 1;
 125         rcba_base = rcba_base << 1;
 126         *((volatile u32 *)(rcba_base +0x104)) &= 0xFF00FFFF;
 127 }
 128
 129 static void lpc_init(struct device *dev)
 130 {
 131         printk(BIOS_DEBUG, "SCH: lpc_init\n");
 132
 133         /* Setup the PIRQ. */
 134         sch_pirq_init(dev);
 135         pci_write_config8(dev, SCH_SIRQ_CTL,0x80);
 136         sch_fixups(dev);
 137 }
 138
 139 static void sch_lpc_read_resources(device_t dev)
 140 {
 141         struct resource *res;
 142
 143         /* Get the normal PCI resources of this device. */
 144         pci_dev_read_resources(dev);
 145
 146         /* Add an extra subtractive resource for both memory and I/O. */
 147         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 148         res->base = 0;
 149         res->size = 0xe000;
 150         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 151                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 152
 153         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 154         res->base = 0xff800000;
 155         res->size = 0x00800000; /* 8 MB for flash */
 156         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 157                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 158
 159         res = new_resource(dev, 3); /* IOAPIC */
 160         res->base = 0xfec00000;
 161         res->size = 0x00001000;
 162         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 163 }
 164
 165 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 166 {
 167         if (!vendor || !device) {
 168                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 169                                 pci_read_config32(dev, PCI_VENDOR_ID));
 170         } else {
 171                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 172                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 173         }
 174 }
 175
 176 static struct pci_operations pci_ops = {
 177         .set_subsystem = set_subsystem,
 178 };
 179
 180 static struct device_operations device_ops = {
 181         .read_resources         = sch_lpc_read_resources,
 182         .set_resources          = pci_dev_set_resources,
 183         .enable_resources       = pci_dev_enable_resources,
 184         .init                   = lpc_init,
 185         .scan_bus               = scan_static_bus,
 186         .ops_pci                = &pci_ops,
 187 };
 188
 189 /* SCH LPC Interface */
 190 static const struct pci_driver sch_lpc __pci_driver = {
 191         .ops    = &device_ops,
 192         .vendor = PCI_VENDOR_ID_INTEL,
 193         .device = 0x8119,
 194 };