2 * This file is part of the coreboot project.
4 * Copyright (C) 2009-2010 iWave Systems
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
25 /* PCI Configuration Space (D31:F1): IDE */
27 #define IDE_TIM_PRI 0x80 /* IDE timings, primary */
29 extern int sch_port_access_read(int port, int reg, int bytes);
31 static void ide_init(struct device *dev)
33 u32 ideTimingConfig, reg32;
35 printk(BIOS_DEBUG, "sch_ide: initializing... ");
37 reg32 = pci_read_config32(dev, PCI_COMMAND);
38 pci_write_config32(dev, PCI_COMMAND,
39 reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
41 /* Program the clock. */
42 if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
43 /* 533MHz, Read PCI MC register */
44 reg32 = pci_read_config32(dev, 0x60);
45 pci_write_config32(dev, 0x60, reg32 | 1);
48 reg32 = pci_read_config32(dev, 0x60);
50 pci_write_config32(dev, 0x60, reg32);
53 /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
54 ideTimingConfig = 0x80020000;
55 printk(BIOS_DEBUG, "IDE0 ");
56 pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
58 /* Set Interrupt Line. */
59 /* Interrupt Pin is set by D31IP.PIP */
60 printk(BIOS_DEBUG, "\n");
63 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
65 if (!vendor || !device) {
66 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
67 pci_read_config32(dev, PCI_VENDOR_ID));
69 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
70 ((device & 0xffff) << 16) | (vendor & 0xffff));
74 static struct pci_operations ide_pci_ops = {
75 .set_subsystem = ide_set_subsystem,
78 static struct device_operations ide_ops = {
79 .read_resources = pci_dev_read_resources,
80 .set_resources = pci_dev_set_resources,
81 .enable_resources = pci_dev_enable_resources,
84 .ops_pci = &ide_pci_ops,
87 static const struct pci_driver sch_ide __pci_driver = {
89 .vendor = PCI_VENDOR_ID_INTEL,