1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
5 #include <device/pci_ops.h>
6 #include <pc80/mc146818rtc.h>
10 static int num_p64h2_ioapics = 0;
12 static void p64h2_ioapic_enable(device_t dev)
14 /* We have to enable MEM and Bus Master for IOAPIC */
15 uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
18 pci_write_config16(dev, PCI_COMMAND, command);
22 * Configure one of the IOAPICs in a P64H2.
24 * Note that a PCI bus scan will detect both IOAPICs, so this function
25 * will be called twice for each P64H2 in the system.
27 * @param dev PCI bus/device/function of P64H2 IOAPIC.
28 * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
30 static void p64h2_ioapic_init(device_t dev)
33 int apic_index, apic_id;
35 volatile uint32_t* pIndexRegister; /* io apic io memory space command address */
36 volatile uint32_t* pWindowRegister; /* io apic io memory space data address */
38 apic_index = num_p64h2_ioapics;
41 // A note on IOAPIC addresses:
42 // 0 and 1 are used for the local APICs of the dual virtual
43 // (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb).
44 // 6 and 7 are used for the local APICs of the dual virtual
45 // (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb).
46 // 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c)
48 // Map APIC index into APIC ID
49 // IDs 3, 4, 5, and 8+ are available (see above note)
52 apic_id = apic_index + 3;
54 apic_id = apic_index + 5;
56 ASSERT(apic_id < 16); // ID is only 4 bits
58 // Read the MBAR address for setting up the IOAPIC in memory space
59 // NOTE: this address was assigned during enumeration of the bus
61 memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
62 pIndexRegister = (volatile uint32_t*) memoryBase;
63 pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
65 printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
66 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
67 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
69 apic_id <<= 24; // Convert ID to bitmask
71 *pIndexRegister = 0; // Select APIC ID register
72 *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
74 if ((*pWindowRegister & (0xF<<24)) != apic_id)
75 die("p64h2_ioapic_init failed");
77 *pIndexRegister = 3; // Select Boot Configuration register
78 *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
80 if (!(*pWindowRegister & 1))
81 die("p64h2_ioapic_init failed");
84 static struct device_operations ioapic_ops = {
85 .read_resources = pci_dev_read_resources,
86 .set_resources = pci_dev_set_resources,
87 .enable_resources = pci_dev_enable_resources,
88 .init = p64h2_ioapic_init,
90 .enable = p64h2_ioapic_enable,
93 static const struct pci_driver ioapic_driver __pci_driver = {
95 .vendor = PCI_VENDOR_ID_INTEL,
96 .device = PCI_DEVICE_ID_INTEL_82870_1E0,