2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/smbus_def.h>
23 static void smbus_delay(void)
28 static int smbus_wait_until_ready(void)
30 unsigned loops = SMBUS_TIMEOUT;
36 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
38 return loops ? 0 : -1;
41 static int smbus_wait_until_done(void)
43 unsigned loops = SMBUS_TIMEOUT;
49 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
50 } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
51 return loops ? 0 : -1;
54 static int smbus_wait_until_blk_done(void)
56 unsigned loops = SMBUS_TIMEOUT;
62 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
63 } while ((byte & (1 << 7)) == 0);
64 return loops ? 0 : -1;
67 static int do_smbus_read_byte(unsigned device, unsigned address)
69 unsigned char global_status_register;
72 if (smbus_wait_until_ready() < 0) {
73 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
75 /* Setup transaction */
76 /* Disable interrupts */
77 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
78 /* Set the device I'm talking too */
79 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
80 /* Set the command/address... */
81 outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
82 /* Set up for a byte data read */
83 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
84 (SMBUS_IO_BASE + SMBHSTCTL));
85 /* Clear any lingering errors, so the transaction will run */
86 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
88 /* Clear the data byte... */
89 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
91 /* Start the command */
92 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
93 SMBUS_IO_BASE + SMBHSTCTL);
95 /* Poll for transaction completion */
96 if (smbus_wait_until_done() < 0) {
97 return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
100 global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
102 /* Ignore the "In Use" status... */
103 global_status_register &= ~(3 << 5);
105 /* Read results of transaction */
106 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
107 if (global_status_register != (1 << 1)) {
113 /* This function is neither used nor tested by me (Corey Osgood), the author
114 (Yinghai) probably tested/used it on i82801er */
115 static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
116 unsigned data1, unsigned data2)
118 #warning "do_smbus_write_block is commented out"
119 print_err("Untested smbus_write_block called\r\n");
121 unsigned char global_control_register;
122 unsigned char global_status_register;
127 /* Clear the PM timeout flags, SECOND_TO_STS */
128 outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
130 if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
134 /* Setup transaction */
135 /* Obtain ownership */
136 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
137 for (stat = 0; (stat & 0x40) == 0;) {
138 stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
140 /* Clear the done bit */
141 outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
142 /* Disable interrupts */
143 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
145 /* Set the device I'm talking too */
146 outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
148 /* Set the command address */
149 outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
151 /* Set the block length */
152 outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0);
154 /* Try sending out the first byte of data here */
155 byte = (data1 >> (0)) & 0x0ff;
156 outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
157 /* Issue a block write command */
158 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
159 SMBUS_IO_BASE + SMBHSTCTL);
161 for (i = 0; i < length; i++) {
163 /* Poll for transaction completion */
164 if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
168 /* Load the next byte */
170 byte = (data2 >> (i % 4)) & 0x0ff;
172 byte = (data1 >> (i)) & 0x0ff;
173 outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
175 /* Clear the done bit */
176 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
177 SMBUS_IO_BASE + SMBHSTSTAT);
180 print_debug("SMBUS Block complete\r\n");