2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 #include <arch/romcc_io.h>
25 #include <console/console.h>
26 #include <cpu/x86/cache.h>
27 #include <cpu/x86/smm.h>
28 #include <device/pci_def.h>
32 #define CST_CONTROL 0x85
33 #define PST_CONTROL 0x80
34 #define ACPI_DISABLE 0x1e
35 #define ACPI_ENABLE 0xe1
36 #define GNVS_UPDATE 0xea
41 #define D_OPEN (1 << 6)
42 #define D_CLS (1 << 5)
43 #define D_LCK (1 << 4)
44 #define G_SMRANE (1 << 3)
45 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
49 /* While we read PMBASE dynamically in case it changed, let's
50 * initialize it with a sane value
52 u16 pmbase = DEFAULT_PMBASE;
53 u8 smm_initialized = 0;
55 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
58 global_nvs_t *gnvs = (global_nvs_t *)0x0;
59 void *tcg = (void *)0x0;
60 void *smi1 = (void *)0x0;
63 * @brief read and clear PM1_STS
64 * @return PM1_STS register
66 static u16 reset_pm1_status(void)
70 reg16 = inw(pmbase + PM1_STS);
71 /* set status bits are cleared by writing 1 to them */
72 outw(reg16, pmbase + PM1_STS);
77 static void dump_pm1_status(u16 pm1_sts)
79 printk(BIOS_SPEW, "PM1_STS: ");
80 if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
81 if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
82 if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
83 if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
84 if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
85 if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
86 if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
87 if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
88 printk(BIOS_SPEW, "\n");
89 int reg16 = inw(pmbase + PM1_EN);
90 printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
94 * @brief read and clear SMI_STS
95 * @return SMI_STS register
97 static u32 reset_smi_status(void)
101 reg32 = inl(pmbase + SMI_STS);
102 /* set status bits are cleared by writing 1 to them */
103 outl(reg32, pmbase + SMI_STS);
108 static void dump_smi_status(u32 smi_sts)
110 printk(BIOS_DEBUG, "SMI_STS: ");
111 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
112 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
113 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
114 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
115 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
116 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
117 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
118 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
119 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
120 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
121 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
122 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
123 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
124 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
125 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
126 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
127 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
128 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
129 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
130 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
131 printk(BIOS_DEBUG, "\n");
136 * @brief read and clear GPE0_STS
137 * @return GPE0_STS register
139 static u32 reset_gpe0_status(void)
143 reg32 = inl(pmbase + GPE0_STS);
144 /* set status bits are cleared by writing 1 to them */
145 outl(reg32, pmbase + GPE0_STS);
150 static void dump_gpe0_status(u32 gpe0_sts)
153 printk(BIOS_DEBUG, "GPE0_STS: ");
154 for (i=31; i<= 16; i--) {
155 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
157 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
158 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
159 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
160 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
161 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
162 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
163 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
164 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
165 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
166 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
167 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
168 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
169 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
170 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
171 printk(BIOS_DEBUG, "\n");
176 * @brief read and clear TCOx_STS
177 * @return TCOx_STS registers
179 static u32 reset_tco_status(void)
181 u32 tcobase = pmbase + 0x60;
184 reg32 = inl(tcobase + 0x04);
185 /* set status bits are cleared by writing 1 to them */
186 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
187 if (reg32 & (1 << 18))
188 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
194 static void dump_tco_status(u32 tco_sts)
196 printk(BIOS_DEBUG, "TCO_STS: ");
197 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
198 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
199 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
200 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
201 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
202 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
203 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
204 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
205 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
206 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
207 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
208 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
209 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
210 printk(BIOS_DEBUG, "\n");
213 /* We are using PCIe accesses for now
214 * 1. the chipset can do it
215 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
217 #include "../../../northbridge/intel/i945/pcie_config.c"
219 int southbridge_io_trap_handler(int smif)
223 printk(BIOS_DEBUG, "OS Init\n");
225 * On success, the IO Trap Handler returns 0
226 * On failure, the IO Trap Handler returns a value != 0
229 return 1; /* IO trap handled */
237 * @brief Set the EOS bit
239 void southbridge_smi_set_eos(void)
243 reg8 = inb(pmbase + SMI_EN);
245 outb(reg8, pmbase + SMI_EN);
248 static void busmaster_disable_on_bus(int bus)
254 for (slot = 0; slot < 0x20; slot++) {
255 for (func = 0; func < 8; func++) {
257 device_t dev = PCI_DEV(bus, slot, func);
259 val = pci_read_config32(dev, PCI_VENDOR_ID);
261 if (val == 0xffffffff || val == 0x00000000 ||
262 val == 0x0000ffff || val == 0xffff0000)
265 /* Disable Bus Mastering for this one device */
266 reg32 = pci_read_config32(dev, PCI_COMMAND);
267 reg32 &= ~PCI_COMMAND_MASTER;
268 pci_write_config32(dev, PCI_COMMAND, reg32);
270 /* If this is a bridge, then follow it. */
271 hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
273 if (hdr == PCI_HEADER_TYPE_BRIDGE ||
274 hdr == PCI_HEADER_TYPE_CARDBUS) {
276 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
277 busmaster_disable_on_bus((buses >> 8) & 0xff);
284 static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
289 /* FIXME: the power state on boot should be read from
290 * CMOS or even better from GNVS. Right now it's hard
291 * coded at compile time.
293 u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
295 /* First, disable further SMIs */
296 reg8 = inb(pmbase + SMI_EN);
298 outb(reg8, pmbase + SMI_EN);
300 /* Figure out SLP_TYP */
301 reg32 = inl(pmbase + PM1_CNT);
302 printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
303 slp_typ = (reg32 >> 10) & 7;
305 /* Next, do the deed.
309 case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
310 case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
312 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
313 /* Invalidate the cache before going to S3 */
316 case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
318 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
320 outl(0, pmbase + GPE0_EN);
322 /* Should we keep the power state after a power loss?
323 * In case the setting is "ON" or "OFF" we don't have
324 * to do anything. But if it's "KEEP" we have to switch
325 * to "OFF" before entering S5.
327 if (s5pwr == MAINBOARD_POWER_KEEP) {
328 reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
330 pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
333 /* also iterates over all bridges on bus 0 */
334 busmaster_disable_on_bus(0);
336 default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
339 /* Write back to the SLP register to cause the originally intended
340 * event again. We need to set BIT13 (SLP_EN) though to make the
343 outl(reg32 | SLP_EN, pmbase + PM1_CNT);
345 /* In most sleep states, the code flow of this function ends at
346 * the line above. However, if we entered sleep state S1 and wake
347 * up again, we will continue to execute code in this function.
349 reg32 = inl(pmbase + PM1_CNT);
350 if (reg32 & SCI_EN) {
351 /* The OS is not an ACPI OS, so we set the state to S0 */
352 reg32 &= ~(SLP_EN | SLP_TYP);
353 outl(reg32, pmbase + PM1_CNT);
357 static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
362 /* Emulate B2 register as the FADT / Linux expects it */
365 if (mainboard_apm_cnt && mainboard_apm_cnt(reg8))
370 /* Calling this function seems to cause
371 * some kind of race condition in Linux
372 * and causes a kernel oops
374 printk(BIOS_DEBUG, "C-state control\n");
377 /* Calling this function seems to cause
378 * some kind of race condition in Linux
379 * and causes a kernel oops
381 printk(BIOS_DEBUG, "P-state control\n");
384 pmctrl = inl(pmbase + PM1_CNT);
386 outl(pmctrl, pmbase + PM1_CNT);
387 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
390 pmctrl = inl(pmbase + PM1_CNT);
392 outl(pmctrl, pmbase + PM1_CNT);
393 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
396 if (smm_initialized) {
397 printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
400 gnvs = *(global_nvs_t **)0x500;
401 tcg = *(void **)0x504;
402 smi1 = *(void **)0x508;
404 printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
407 printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
411 static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
415 pm1_sts = reset_pm1_status();
416 dump_pm1_status(pm1_sts);
418 /* While OSPM is not active, poweroff immediately
419 * on a power button event.
421 if (pm1_sts & PWRBTN_STS) {
422 // power button pressed
424 reg32 = (7 << 10) | (1 << 13);
425 outl(reg32, pmbase + PM1_CNT);
429 static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
433 gpe0_sts = reset_gpe0_status();
434 dump_gpe0_status(gpe0_sts);
437 static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
440 reg16 = inw(pmbase + ALT_GP_SMI_STS);
441 outl(reg16, pmbase + ALT_GP_SMI_STS);
443 reg16 &= inw(pmbase + ALT_GP_SMI_EN);
445 if (mainboard_smi_gpi) {
446 mainboard_smi_gpi(reg16);
449 printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
453 static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
457 reg32 = inl(pmbase + SMI_EN);
459 /* Are periodic SMIs enabled? */
460 if ((reg32 & MCSMI_EN) == 0)
463 printk(BIOS_DEBUG, "Microcontroller SMI.\n");
468 static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
472 tco_sts = reset_tco_status();
478 if (tco_sts & (1 << 8)) { // BIOSWR
481 bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
484 /* BWE is RW, so the SMI was caused by a
485 * write to BWE, not by a write to the BIOS
488 /* This is the place where we notice someone
489 * is trying to tinker with the BIOS. We are
490 * trying to be nice and just ignore it. A more
491 * resolute answer would be to power down the
494 printk(BIOS_DEBUG, "Switching back to RO\n");
495 pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
496 } /* No else for now? */
497 } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
498 /* Handle TCO timeout */
499 printk(BIOS_DEBUG, "TCO Timeout.\n");
500 } else if (!tco_sts) {
501 dump_tco_status(tco_sts);
505 static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
509 reg32 = inl(pmbase + SMI_EN);
511 /* Are periodic SMIs enabled? */
512 if ((reg32 & PERIODIC_EN) == 0)
515 printk(BIOS_DEBUG, "Periodic SMI.\n");
518 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
520 #define IOTRAP(x) (trap_sts & (1 << x))
521 u32 trap_sts, trap_cycle;
525 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
526 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
528 trap_cycle = RCBA32(0x1e10);
529 for (i=16; i<20; i++) {
530 if (trap_cycle & (1 << i))
531 mask |= (0xff << ((i - 16) << 2));
535 /* IOTRAP(3) SMI function call */
537 if (gnvs && gnvs->smif)
538 io_trap_handler(gnvs->smif); // call function smif
542 /* IOTRAP(2) currently unused
543 * IOTRAP(1) currently unused */
547 if (!(trap_cycle & (1 << 24))) { // It's a write
548 printk(BIOS_DEBUG, "SMI1 command\n");
549 data = RCBA32(0x1e18);
552 // southbridge_smi_command(data);
555 // Fall through to debug
558 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
559 for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPĀ = %d\n", i);
560 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
561 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
562 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
564 if (!(trap_cycle & (1 << 24))) {
566 data = RCBA32(0x1e18);
567 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
572 typedef void (*smi_handler_t)(unsigned int node,
573 smm_state_save_area_t *state_save);
575 smi_handler_t southbridge_smi[32] = {
576 NULL, // [0] reserved
577 NULL, // [1] reserved
578 NULL, // [2] BIOS_STS
579 NULL, // [3] LEGACY_USB_STS
580 southbridge_smi_sleep, // [4] SLP_SMI_STS
581 southbridge_smi_apmc, // [5] APM_STS
582 NULL, // [6] SWSMI_TMR_STS
583 NULL, // [7] reserved
584 southbridge_smi_pm1, // [8] PM1_STS
585 southbridge_smi_gpe0, // [9] GPE0_STS
586 southbridge_smi_gpi, // [10] GPI_STS
587 southbridge_smi_mc, // [11] MCSMI_STS
588 NULL, // [12] DEVMON_STS
589 southbridge_smi_tco, // [13] TCO_STS
590 southbridge_smi_periodic, // [14] PERIODIC_STS
591 NULL, // [15] SERIRQ_SMI_STS
592 NULL, // [16] SMBUS_SMI_STS
593 NULL, // [17] LEGACY_USB2_STS
594 NULL, // [18] INTEL_USB2_STS
595 NULL, // [19] reserved
596 NULL, // [20] PCI_EXP_SMI_STS
597 southbridge_smi_monitor, // [21] MONITOR_STS
598 NULL, // [22] reserved
599 NULL, // [23] reserved
600 NULL, // [24] reserved
601 NULL, // [25] EL_SMI_STS
602 NULL, // [26] SPI_STS
603 NULL, // [27] reserved
604 NULL, // [28] reserved
605 NULL, // [29] reserved
606 NULL, // [30] reserved
607 NULL // [31] reserved
611 * @brief Interrupt handler for SMI#
613 * @param smm_revision revision of the smm state save map
616 void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
621 /* Update global variable pmbase */
622 pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
624 /* We need to clear the SMI status registers, or we won't see what's
625 * happening in the following calls.
627 smi_sts = reset_smi_status();
629 /* Filter all non-enabled SMI events */
630 // FIXME Double check, this clears MONITOR
631 // smi_sts &= inl(pmbase + SMI_EN);
633 /* Call SMI sub handler for each of the status bits */
634 for (i = 0; i < 31; i++) {
635 if (smi_sts & (1 << i)) {
636 if (southbridge_smi[i])
637 southbridge_smi[i](node, state_save);
639 printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
640 "handler available.\n", i);
647 dump_smi_status(smi_sts);