src/southbridge/intel/i82801gx/pci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 static void pci_init(struct device *dev)
  28 {
  29         u16 reg16;
  30         u8 reg8;
  31
  32         /* Enable Bus Master */
  33         reg16 = pci_read_config16(dev, PCI_COMMAND);
  34         reg16 |= PCI_COMMAND_MASTER;
  35         pci_write_config16(dev, PCI_COMMAND, reg16);
  36
  37         /* This device has no interrupt */
  38         pci_write_config8(dev, INTR, 0xff);
  39
  40         /* disable parity error response and SERR */
  41         reg16 = pci_read_config16(dev, BCTRL);
  42         reg16 &= ~(1 << 0);
  43         reg16 &= ~(1 << 1);
  44         pci_write_config16(dev, BCTRL, reg16);
  45
  46         /* Master Latency Count must be set to 0x04! */
  47         reg8 = pci_read_config8(dev, SMLT);
  48         reg8 &= 0x07;
  49         reg8 |= (0x04 << 3);
  50         pci_write_config8(dev, SMLT, reg8);
  51
  52         /* Will this improve throughput of bus masters? */
  53         pci_write_config8(dev, PCI_MIN_GNT, 0x06);
  54
  55         /* Clear errors in status registers */
  56         reg16 = pci_read_config16(dev, PSTS);
  57         //reg16 |= 0xf900;
  58         pci_write_config16(dev, PSTS, reg16);
  59
  60         reg16 = pci_read_config16(dev, SECSTS);
  61         // reg16 |= 0xf900;
  62         pci_write_config16(dev, SECSTS, reg16);
  63 }
  64
  65 #undef PCI_BRIDGE_UPDATE_COMMAND
  66 static void ich_pci_dev_enable_resources(struct device *dev)
  67 {
  68         const struct pci_operations *ops;
  69         uint16_t command;
  70
  71         /* Set the subsystem vendor and device id for mainboard devices */
  72         ops = ops_pci(dev);
  73         if (dev->on_mainboard && ops && ops->set_subsystem) {
  74                 printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
  75                        dev_path(dev), dev->subsystem_vendor,
  76                        dev->subsystem_device);
  77                 ops->set_subsystem(dev, dev->subsystem_vendor,
  78                                    dev->subsystem_device);
  79         }
  80
  81         command = pci_read_config16(dev, PCI_COMMAND);
  82         command |= dev->command;
  83 #ifdef PCI_BRIDGE_UPDATE_COMMAND
  84         /* If we write to PCI_COMMAND, on some systems
  85          * this will cause the ROM and APICs not being visible
  86          * anymore.
  87          */
  88         printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
  89         pci_write_config16(dev, PCI_COMMAND, command);
  90 #else
  91         printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
  92 #endif
  93 }
  94
  95 static void ich_pci_bus_enable_resources(struct device *dev)
  96 {
  97         uint16_t ctrl;
  98         /* enable IO in command register if there is VGA card
  99          * connected with (even it does not claim IO resource)
 100          */
 101         if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 102                 dev->command |= PCI_COMMAND_IO;
 103         ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 104         ctrl |= dev->link_list->bridge_ctrl;
 105         ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
 106         printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 107         pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 108
 109         /* This is the reason we need our own pci_bus_enable_resources */
 110         ich_pci_dev_enable_resources(dev);
 111 }
 112
 113 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 114 {
 115         /* NOTE: This is not the default position! */
 116         if (!vendor || !device) {
 117                 pci_write_config32(dev, 0x54,
 118                                 pci_read_config32(dev, PCI_VENDOR_ID));
 119         } else {
 120                 pci_write_config32(dev, 0x54,
 121                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 122         }
 123 }
 124
 125 static struct pci_operations pci_ops = {
 126         .set_subsystem = set_subsystem,
 127 };
 128
 129 static struct device_operations device_ops = {
 130         .read_resources         = pci_bus_read_resources,
 131         .set_resources          = pci_dev_set_resources,
 132         .enable_resources       = ich_pci_bus_enable_resources,
 133         .init                   = pci_init,
 134         .scan_bus               = pci_scan_bridge,
 135         .ops_pci                = &pci_ops,
 136 };
 137
 138 /* Desktop */
 139 /* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
 140 static const struct pci_driver i82801g_pci __pci_driver = {
 141         .ops    = &device_ops,
 142         .vendor = PCI_VENDOR_ID_INTEL,
 143         .device = 0x244e,
 144 };
 145
 146 /* Mobile / Ultra Mobile */
 147 /* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
 148 static const struct pci_driver i82801gmu_pci __pci_driver = {
 149         .ops    = &device_ops,
 150         .vendor = PCI_VENDOR_ID_INTEL,
 151         .device = 0x2448,
 152 };