src/southbridge/intel/i82801gx/i82801gx_usb.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 static void usb_init(struct device *dev)
  28 {
  29         u32 reg32;
  30         u8 reg8;
  31
  32         /* USB Specification says the device must be Bus Master */
  33         printk_debug("UHCI: Setting up controller.. ");
  34
  35         reg32 = pci_read_config32(dev, PCI_COMMAND);
  36         pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
  37
  38         reg8 = pci_read_config8(dev, 0xca);
  39         reg8 |= (1 << 0);
  40         pci_write_config8(dev, 0xca, reg8);
  41
  42         printk_debug("done.\n");
  43 }
  44
  45 static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  46 {
  47         if (!vendor || !device) {
  48                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  49                                 pci_read_config32(dev, PCI_VENDOR_ID));
  50         } else {
  51                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  52                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  53         }
  54 }
  55
  56 static struct pci_operations usb_pci_ops = {
  57         .set_subsystem    = usb_set_subsystem,
  58 };
  59
  60 static struct device_operations usb_ops = {
  61         .read_resources         = pci_dev_read_resources,
  62         .set_resources          = pci_dev_set_resources,
  63         .enable_resources       = pci_dev_enable_resources,
  64         .init                   = usb_init,
  65         .scan_bus               = 0,
  66         .enable                 = i82801gx_enable,
  67         .ops_pci                = &usb_pci_ops,
  68 };
  69
  70 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  71 static const struct pci_driver i82801gb_usb1 __pci_driver = {
  72         .ops    = &usb_ops,
  73         .vendor = PCI_VENDOR_ID_INTEL,
  74         .device = 0x27c8,
  75 };
  76
  77 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  78 static const struct pci_driver i82801gb_usb2 __pci_driver = {
  79         .ops    = &usb_ops,
  80         .vendor = PCI_VENDOR_ID_INTEL,
  81         .device = 0x27c9,
  82 };
  83
  84 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  85 static const struct pci_driver i82801gb_usb3 __pci_driver = {
  86         .ops    = &usb_ops,
  87         .vendor = PCI_VENDOR_ID_INTEL,
  88         .device = 0x27ca,
  89 };
  90
  91 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  92 static const struct pci_driver i82801gb_usb4 __pci_driver = {
  93         .ops    = &usb_ops,
  94         .vendor = PCI_VENDOR_ID_INTEL,
  95         .device = 0x27cb,
  96 };