src/southbridge/intel/i82801gx/i82801gx_sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 typedef struct southbridge_intel_i82801gx_config config_t;
  28
  29 static void sata_init(struct device *dev)
  30 {
  31         u32 reg32;
  32         /* Get the chip configuration */
  33         config_t *config = dev->chip_info;
  34
  35         printk_debug("i82801gx_sata: initializing...\n");
  36         /* SATA configuration */
  37
  38         /* Enable BARs */
  39         pci_write_config16(dev, 0x04, 0x0007);
  40
  41         if (config->ide_legacy_combined) {
  42                 pci_write_config8(dev, 0x09, 0x80);
  43
  44                 /* Set timings */
  45                 pci_write_config16(dev, IDE_TIM_PRI, 0x8000);
  46                 pci_write_config16(dev, IDE_TIM_SEC, 0xa307);
  47
  48                 /* Sync DMA */
  49                 pci_write_config16(dev, 0x48, 0x0004);
  50                 pci_write_config16(dev, 0x4a, 0x0200);
  51
  52                 /* Combine IDE - SATA configuration */
  53                 pci_write_config8(dev, 0x90, 0x02);
  54
  55                 /* Port 0 & 1 enable */
  56                 pci_write_config8(dev, 0x92, 0x0f);
  57
  58                 /* SATA Initialization register */
  59                 pci_write_config32(dev, 0x94, 0x40000180);
  60         } else if(config->sata_ahci) {
  61                 /* Allow both Legacy and Native mode */
  62                 pci_write_config8(dev, 0x09, 0x8f);
  63
  64                 /* Set Interrupt Line */
  65                 /* Interrupt Pin is set by D31IP.PIP */
  66                 pci_write_config8(dev, INTR_LN, 0x0a);
  67
  68                 /* Set timings */
  69                 pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
  70                 pci_write_config16(dev, IDE_TIM_SEC, 0x8000);
  71
  72                 /* Sync DMA */
  73                 pci_write_config16(dev, 0x48, 0x0001);
  74                 pci_write_config16(dev, 0x4a, 0x0001);
  75
  76                 /* Set IDE I/O Configuration */
  77                 reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  78                 pci_write_config32(dev, IDE_CONFIG, reg32);
  79
  80                 /* Set Sata Controller Mode. */
  81                 pci_write_config8(dev, 0x90, 0xc0); // WTF - Reserved?
  82
  83                 /* Port 0 & 1 enable */
  84                 pci_write_config8(dev, 0x92, 0x0f);
  85
  86                 /* SATA Initialization register */
  87                 pci_write_config32(dev, 0x94, 0x1a000180);
  88         } else {
  89                 /* Native mode capable on both primary and secondary (0xa)
  90                  * or'ed with enabled (0x50) = 0xf
  91                  */
  92                 pci_write_config8(dev, 0x09, 0x8f);
  93
  94                 /* Set Interrupt Line */
  95                 /* Interrupt Pin is set by D31IP.PIP */
  96                 pci_write_config8(dev, INTR_LN, 0xff);
  97
  98                 /* Set timings */
  99                 pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
 100                 pci_write_config16(dev, IDE_TIM_SEC, 0xe303);
 101
 102                 /* Sync DMA */
 103                 pci_write_config16(dev, 0x48, 0x0005);
 104                 pci_write_config16(dev, 0x4a, 0x0201);
 105
 106                 /* Set IDE I/O Configuration */
 107                 reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 108                 pci_write_config32(dev, IDE_CONFIG, reg32);
 109
 110                 /* Set Sata Controller Mode. */
 111                 pci_write_config8(dev, 0x90, 0x02);
 112
 113                 /* Port 0 & 1 enable XXX */
 114                 pci_write_config8(dev, 0x92, 0x15);
 115
 116                 /* SATA Initialization register */
 117                 pci_write_config32(dev, 0x94, 0x1a000180);
 118         }
 119
 120         /* All configurations need this SATA initialization sequence */
 121         pci_write_config8(dev, 0xa0, 0x40);
 122         pci_write_config8(dev, 0xa6, 0x22);
 123         pci_write_config8(dev, 0xa0, 0x78);
 124         pci_write_config8(dev, 0xa6, 0x22);
 125         pci_write_config8(dev, 0xa0, 0x88);
 126         reg32 = pci_read_config32(dev, 0xa4);
 127         reg32 &= 0xc0c0c0c0;
 128         reg32 |= 0x1b1b1212;
 129         pci_write_config32(dev, 0xa4, reg32);
 130         pci_write_config8(dev, 0xa0, 0x8c);
 131         reg32 = pci_read_config32(dev, 0xa4);
 132         reg32 &= 0xc0c0ff00;
 133         reg32 |= 0x121200aa;
 134         pci_write_config32(dev, 0xa4, reg32);
 135         pci_write_config8(dev, 0xa0, 0x00);
 136
 137         pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 138 }
 139
 140 static struct device_operations sata_ops = {
 141         .read_resources         = pci_dev_read_resources,
 142         .set_resources          = pci_dev_set_resources,
 143         .enable_resources       = pci_dev_enable_resources,
 144         .init                   = sata_init,
 145         .scan_bus               = 0,
 146         .enable                 = i82801gx_enable,
 147 };
 148
 149 /* Desktop Non-AHCI and Non-RAID Mode */
 150 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 151 static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = {
 152         .ops    = &sata_ops,
 153         .vendor = PCI_VENDOR_ID_INTEL,
 154         .device = 0x27c0,
 155 };
 156
 157 /* NOTE: Any of the below are not properly supported yet. */
 158
 159 /* Desktop AHCI Mode */
 160 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 161 static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = {
 162         .ops    = &sata_ops,
 163         .vendor = PCI_VENDOR_ID_INTEL,
 164         .device = 0x27c1,
 165 };
 166
 167 /* Desktop RAID mode */
 168 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 169 static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = {
 170         .ops    = &sata_ops,
 171         .vendor = PCI_VENDOR_ID_INTEL,
 172         .device = 0x27c3,
 173 };
 174
 175 /* Mobile Non-AHCI and Non-RAID Mode */
 176 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 177 static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = {
 178         .ops    = &sata_ops,
 179         .vendor = PCI_VENDOR_ID_INTEL,
 180         .device = 0x27c4,
 181 };
 182
 183 /* Mobile AHCI Mode */
 184 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 185 static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = {
 186         .ops    = &sata_ops,
 187         .vendor = PCI_VENDOR_ID_INTEL,
 188         .device = 0x27c5,
 189 };
 190
 191 /* ICH7M DH Raid Mode */
 192 /* 82801GHM (ICH7-M DH) */
 193 static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = {
 194         .ops    = &sata_ops,
 195         .vendor = PCI_VENDOR_ID_INTEL,
 196         .device = 0x27c6,
 197 };