src/southbridge/intel/i82801gx/i82801gx_sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 typedef struct southbridge_intel_i82801gx_config config_t;
  28
  29 static void sata_init(struct device *dev)
  30 {
  31         u32 reg32;
  32         u16 reg16;
  33         /* Get the chip configuration */
  34         config_t *config = dev->chip_info;
  35
  36         printk_debug("i82801gx_sata: initializing...\n");
  37
  38         if (config == NULL)
  39                 printk_err("i82801gx_sata: error: device not in Config.lb!\n");
  40
  41         /* SATA configuration */
  42
  43         /* Enable BARs */
  44         pci_write_config16(dev, PCI_COMMAND, 0x0007);
  45
  46         if (config->ide_legacy_combined) {
  47                 printk_debug("SATA controller in combined mode.\n");
  48                 /* No AHCI: clear AHCI base */
  49                 pci_write_config32(dev, 0x24, 0x00000000);
  50                 /* And without AHCI BAR no memory decoding */
  51                 reg16 = pci_read_config16(dev, PCI_COMMAND);
  52                 reg16 &= ~PCI_COMMAND_MEMORY;
  53                 pci_write_config16(dev, PCI_COMMAND, reg16);
  54
  55                 pci_write_config8(dev, 0x09, 0x80);
  56
  57                 /* Set timings */
  58                 pci_write_config16(dev, IDE_TIM_PRI, 0x8000);
  59                 pci_write_config16(dev, IDE_TIM_SEC, 0xa307);
  60
  61                 /* Sync DMA */
  62                 pci_write_config16(dev, 0x48, 0x0004);
  63                 pci_write_config16(dev, 0x4a, 0x0200);
  64
  65                 /* Set IDE I/O Configuration */
  66                 reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  67                 pci_write_config32(dev, IDE_CONFIG, reg32);
  68
  69                 /* Combine IDE - SATA configuration */
  70                 pci_write_config8(dev, 0x90, 0x02);
  71
  72                 /* Port 0 & 1 enable */
  73                 pci_write_config8(dev, 0x92, 0x0f);
  74
  75                 /* SATA Initialization register */
  76                 pci_write_config32(dev, 0x94, 0x5a000180);
  77         } else if(config->sata_ahci) {
  78                 printk_debug("SATA controller in AHCI mode.\n");
  79                 /* Allow both Legacy and Native mode */
  80                 pci_write_config8(dev, 0x09, 0x8f);
  81
  82                 /* Set Interrupt Line */
  83                 /* Interrupt Pin is set by D31IP.PIP */
  84                 pci_write_config8(dev, INTR_LN, 0x0a);
  85
  86                 /* Set timings */
  87                 pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
  88                 pci_write_config16(dev, IDE_TIM_SEC, 0x8000);
  89
  90                 /* Sync DMA */
  91                 pci_write_config16(dev, 0x48, 0x0001);
  92                 pci_write_config16(dev, 0x4a, 0x0001);
  93
  94                 /* Set IDE I/O Configuration */
  95                 reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  96                 pci_write_config32(dev, IDE_CONFIG, reg32);
  97
  98                 /* Set Sata Controller Mode. */
  99                 pci_write_config8(dev, 0x90, 0xc0); // WTF - Reserved?
 100
 101                 /* Port 0 & 1 enable */
 102                 pci_write_config8(dev, 0x92, 0x0f);
 103
 104                 /* SATA Initialization register */
 105                 pci_write_config32(dev, 0x94, 0x1a000180);
 106         } else {
 107                 printk_debug("SATA controller in plain mode.\n");
 108                 /* Set Sata Controller Mode. No Mapping(?) */
 109                 pci_write_config8(dev, 0x90, 0x00);
 110
 111                 /* No AHCI: clear AHCI base */
 112                 pci_write_config32(dev, 0x24, 0x00000000);
 113
 114                 /* And without AHCI BAR no memory decoding */
 115                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 116                 reg16 &= ~PCI_COMMAND_MEMORY;
 117                 pci_write_config16(dev, PCI_COMMAND, reg16);
 118
 119                 /* Native mode capable on both primary and secondary (0xa)
 120                  * or'ed with enabled (0x50) = 0xf
 121                  */
 122                 pci_write_config8(dev, 0x09, 0x8f);
 123
 124                 /* Set Interrupt Line */
 125                 /* Interrupt Pin is set by D31IP.PIP */
 126                 pci_write_config8(dev, INTR_LN, 0xff);
 127
 128                 /* Set timings */
 129                 pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
 130                 pci_write_config16(dev, IDE_TIM_SEC, 0xe303);
 131
 132                 /* Sync DMA */
 133                 pci_write_config16(dev, 0x48, 0x0005);
 134                 pci_write_config16(dev, 0x4a, 0x0201);
 135
 136                 /* Set IDE I/O Configuration */
 137                 reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 138                 pci_write_config32(dev, IDE_CONFIG, reg32);
 139
 140                 /* Port 0 & 1 enable XXX */
 141                 pci_write_config8(dev, 0x92, 0x15);
 142
 143                 /* SATA Initialization register */
 144                 pci_write_config32(dev, 0x94, 0x1a000180);
 145         }
 146
 147         /* All configurations need this SATA initialization sequence */
 148         pci_write_config8(dev, 0xa0, 0x40);
 149         pci_write_config8(dev, 0xa6, 0x22);
 150         pci_write_config8(dev, 0xa0, 0x78);
 151         pci_write_config8(dev, 0xa6, 0x22);
 152         pci_write_config8(dev, 0xa0, 0x88);
 153         reg32 = pci_read_config32(dev, 0xa4);
 154         reg32 &= 0xc0c0c0c0;
 155         reg32 |= 0x1b1b1212;
 156         pci_write_config32(dev, 0xa4, reg32);
 157         pci_write_config8(dev, 0xa0, 0x8c);
 158         reg32 = pci_read_config32(dev, 0xa4);
 159         reg32 &= 0xc0c0ff00;
 160         reg32 |= 0x121200aa;
 161         pci_write_config32(dev, 0xa4, reg32);
 162         pci_write_config8(dev, 0xa0, 0x00);
 163
 164         pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 165
 166         /* Sata Initialization Register */
 167         reg32 = pci_read_config32(dev, 0x94);
 168         reg32 |= (1 << 30); // due to some bug
 169         pci_write_config32(dev, 0x94, reg32);
 170 }
 171
 172 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 173 {
 174         if (!vendor || !device) {
 175                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 176                                 pci_read_config32(dev, PCI_VENDOR_ID));
 177         } else {
 178                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 179                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 180         }
 181 }
 182
 183 static struct pci_operations sata_pci_ops = {
 184         .set_subsystem    = sata_set_subsystem,
 185 };
 186
 187 static struct device_operations sata_ops = {
 188         .read_resources         = pci_dev_read_resources,
 189         .set_resources          = pci_dev_set_resources,
 190         .enable_resources       = pci_dev_enable_resources,
 191         .init                   = sata_init,
 192         .scan_bus               = 0,
 193         .enable                 = i82801gx_enable,
 194         .ops_pci                = &sata_pci_ops,
 195 };
 196
 197 /* Desktop Non-AHCI and Non-RAID Mode */
 198 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 199 static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = {
 200         .ops    = &sata_ops,
 201         .vendor = PCI_VENDOR_ID_INTEL,
 202         .device = 0x27c0,
 203 };
 204
 205 /* Mobile Non-AHCI and Non-RAID Mode */
 206 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 207 static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = {
 208         .ops    = &sata_ops,
 209         .vendor = PCI_VENDOR_ID_INTEL,
 210         .device = 0x27c4,
 211 };
 212
 213
 214 /* NOTE: Any of the below are not properly supported yet. */
 215
 216 /* Desktop AHCI Mode */
 217 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 218 static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = {
 219         .ops    = &sata_ops,
 220         .vendor = PCI_VENDOR_ID_INTEL,
 221         .device = 0x27c1,
 222 };
 223
 224 /* Desktop RAID mode */
 225 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 226 static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = {
 227         .ops    = &sata_ops,
 228         .vendor = PCI_VENDOR_ID_INTEL,
 229         .device = 0x27c3,
 230 };
 231
 232 /* Mobile AHCI Mode */
 233 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 234 static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = {
 235         .ops    = &sata_ops,
 236         .vendor = PCI_VENDOR_ID_INTEL,
 237         .device = 0x27c5,
 238 };
 239
 240 /* ICH7M DH Raid Mode */
 241 /* 82801GHM (ICH7-M DH) */
 242 static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = {
 243         .ops    = &sata_ops,
 244         .vendor = PCI_VENDOR_ID_INTEL,
 245         .device = 0x27c6,
 246 };