2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <pc80/mc146818rtc.h>
26 #include <pc80/isa-dma.h>
27 #include <pc80/i8259.h>
31 #include "../../../northbridge/intel/i945/ich7.h"
33 #define MAINBOARD_POWER_OFF 0
34 #define MAINBOARD_POWER_ON 1
36 #ifndef MAINBOARD_POWER_ON_AFTER_FAIL
37 #define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
42 typedef struct southbridge_intel_i82801gx_config config_t;
44 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
45 * 0x00 - 0000 = Reserved
46 * 0x01 - 0001 = Reserved
47 * 0x02 - 0010 = Reserved
53 * 0x08 - 1000 = Reserved
58 * 0x0D - 1101 = Reserved
61 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
62 * 0x80 - The PIRQ is not routed.
74 static void i82801gx_enable_apic(struct device *dev)
78 volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
79 volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
81 /* Enable ACPI I/O and power management. */
82 pci_write_config8(dev, ACPI_CNTL, 0x80);
85 *ioapic_data = (1 << 25);
89 printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
90 if (reg32 != (1 << 25))
93 printk_spew("Dumping IOAPIC registers\n");
96 printk_spew(" reg 0x%04x:", i);
98 printk_spew(" 0x%08x\n", reg32);
101 *ioapic_index = 3; /* Select Boot Configuration register. */
102 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
105 static void i82801gx_enable_serial_irqs(struct device *dev)
107 /* Set packet length and toggle silent mode bit for one frame. */
108 pci_write_config8(dev, SERIRQ_CNTL,
109 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
112 static void i82801gx_pirq_init(device_t dev)
115 /* Get the chip configuration */
116 config_t *config = dev->chip_info;
118 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
119 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
120 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
121 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
123 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
124 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
125 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
126 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
128 /* Eric Biederman once said we should let the OS do this.
129 * I am not so sure anymore he was right.
132 for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
133 u8 int_pin=0, int_line=0;
135 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
138 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
141 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
142 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
143 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
144 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
150 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
154 static void i82801gx_gpi_routing(device_t dev)
156 /* Get the chip configuration */
157 config_t *config = dev->chip_info;
160 /* An array would be much nicer here, or some
161 * other method of doing this.
163 reg32 |= (config->gpi0_routing & 0x03) << 0;
164 reg32 |= (config->gpi1_routing & 0x03) << 2;
165 reg32 |= (config->gpi2_routing & 0x03) << 4;
166 reg32 |= (config->gpi3_routing & 0x03) << 6;
167 reg32 |= (config->gpi4_routing & 0x03) << 8;
168 reg32 |= (config->gpi5_routing & 0x03) << 10;
169 reg32 |= (config->gpi6_routing & 0x03) << 12;
170 reg32 |= (config->gpi7_routing & 0x03) << 14;
171 reg32 |= (config->gpi8_routing & 0x03) << 16;
172 reg32 |= (config->gpi9_routing & 0x03) << 18;
173 reg32 |= (config->gpi10_routing & 0x03) << 20;
174 reg32 |= (config->gpi11_routing & 0x03) << 22;
175 reg32 |= (config->gpi12_routing & 0x03) << 24;
176 reg32 |= (config->gpi13_routing & 0x03) << 26;
177 reg32 |= (config->gpi14_routing & 0x03) << 28;
178 reg32 |= (config->gpi15_routing & 0x03) << 30;
180 pci_write_config32(dev, 0xb8, reg32);
183 static void i82801gx_power_options(device_t dev)
188 int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
191 /* Which state do we want to goto after g3 (power restored)?
195 get_option(&pwr_on, "power_on_after_fail");
196 reg8 = pci_read_config8(dev, GEN_PMCON_3);
203 reg8 |= (3 << 4); /* avoid #S4 assertions */
204 reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
206 pci_write_config8(dev, GEN_PMCON_3, reg8);
207 printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
209 /* Set up NMI on errors. */
211 reg8 &= 0x0f; /* Higher Nibble must be 0 */
212 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
213 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
214 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
218 nmi_option = NMI_OFF;
219 get_option(&nmi_option, "nmi");
221 printk_info ("NMI sources enabled.\n");
222 reg8 &= ~(1 << 7); /* Set NMI. */
224 printk_info ("NMI sources disabled.\n");
225 reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
229 // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
230 reg16 = pci_read_config16(dev, GEN_PMCON_1);
231 reg16 &= ~((3 << 0) | (1 << 10));
232 reg16 |= (1 << 3) | (1 << 5);
233 reg16 |= (1 << 2); // CLKRUN_EN
234 pci_write_config16(dev, GEN_PMCON_1, reg16);
236 // Set the board's GPI routing.
237 i82801gx_gpi_routing(dev);
240 static void i82801gx_configure_cstates(device_t dev)
244 reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
245 reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
246 pci_write_config8(dev, 0xa9, reg8);
248 // Set Deeper Sleep configuration to recommended values
249 reg8 = pci_read_config8(dev, 0xaa);
251 reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
252 reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
253 pci_write_config8(dev, 0xaa, reg8);
256 static void i82801gx_rtc_init(struct device *dev)
261 reg8 = pci_read_config8(dev, GEN_PMCON_3);
262 rtc_failed = reg8 & RTC_BATTERY_DEAD;
264 reg8 &= ~RTC_BATTERY_DEAD;
265 pci_write_config8(dev, GEN_PMCON_3, reg8);
267 printk_debug("rtc_failed = 0x%x\n", rtc_failed);
269 rtc_init(rtc_failed);
272 static void enable_hpet(void)
276 /* Leave HPET at default address, but enable it */
277 reg32 = RCBA32(0x3404);
278 reg32 |= (1 << 7); // HPET Address Enable
279 RCBA32(0x3404) = reg32;
282 static void enable_clock_gating(void)
286 /* Enable Clock Gating for most devices */
287 reg32 = RCBA32(0x341c);
288 reg32 |= (1 << 31); // LPC clock gating
289 reg32 |= (1 << 30); // PATA clock gating
291 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
292 reg32 |= (1 << 23); // AC97 clock gating
293 reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
294 reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
295 reg32 |= (1 << 2); // PCIe clock gating;
296 RCBA32(0x341c) = reg32;
300 static void i82801gx_lock_smm(struct device *dev)
303 #if TEST_SMM_FLASH_LOCKDOWN
307 #if ENABLE_ACPI_MODE_IN_COREBOOT
308 printk_debug("Enabling ACPI via APMC:\n");
309 outb(0xe1, 0xb2); // Enable ACPI mode
310 printk_debug("done.\n");
312 printk_debug("Disabling ACPI via APMC:\n");
313 outb(0x1e, 0xb2); // Disable ACPI mode
314 printk_debug("done.\n");
316 /* Don't allow evil boot loaders, kernels, or
317 * userspace applications to deceive us:
321 #if TEST_SMM_FLASH_LOCKDOWN
323 printk_debug("Locking BIOS to RO... ");
324 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
325 printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
327 reg8 &= ~(1 << 0); /* clear BIOSWE */
328 pci_write_config8(dev, 0xdc, reg8);
329 reg8 |= (1 << 1); /* set BLE */
330 pci_write_config8(dev, 0xdc, reg8);
331 printk_debug("ok.\n");
332 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
333 printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
336 printk_debug("Writing:\n");
337 *(volatile u8 *)0xfff00000 = 0x00;
338 printk_debug("Testing:\n");
339 reg8 |= (1 << 0); /* set BIOSWE */
340 pci_write_config8(dev, 0xdc, reg8);
342 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
343 printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
345 printk_debug("Done.\n");
350 #define SPIBASE 0x3020
351 static void i82801gx_spi_init(void)
355 spicontrol = RCBA16(SPIBASE + 2);
356 spicontrol &= ~(1 << 0); // SPI Access Request
357 RCBA16(SPIBASE + 2) = spicontrol;
360 static void i82801gx_fixups(void)
362 /* This needs to happen after PCI enumeration */
366 static void lpc_init(struct device *dev)
368 printk_debug("i82801gx: lpc_init\n");
370 /* Set the value for PCI command register. */
371 pci_write_config16(dev, PCI_COMMAND, 0x000f);
373 /* IO APIC initialization. */
374 i82801gx_enable_apic(dev);
376 i82801gx_enable_serial_irqs(dev);
378 /* Setup the PIRQ. */
379 i82801gx_pirq_init(dev);
381 /* Setup power options. */
382 i82801gx_power_options(dev);
384 /* Configure Cx state registers */
385 i82801gx_configure_cstates(dev);
387 /* Set the state of the GPIO lines. */
390 /* Initialize the real time clock. */
391 i82801gx_rtc_init(dev);
393 /* Initialize ISA DMA. */
396 /* Initialize the High Precision Event Timers, if present. */
399 /* Initialize Clock Gating */
400 enable_clock_gating();
405 i82801gx_lock_smm(dev);
413 static void i82801gx_lpc_read_resources(device_t dev)
415 struct resource *res;
417 /* Get the normal PCI resources of this device. */
418 pci_dev_read_resources(dev);
420 /* Add an extra subtractive resource for both memory and I/O. */
421 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
423 IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
425 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
427 IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
430 static void i82801gx_lpc_enable_resources(device_t dev)
432 pci_dev_enable_resources(dev);
433 enable_childrens_resources(dev);
436 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
438 if (!vendor || !device) {
439 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
440 pci_read_config32(dev, PCI_VENDOR_ID));
442 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
443 ((device & 0xffff) << 16) | (vendor & 0xffff));
447 static struct pci_operations pci_ops = {
448 .set_subsystem = set_subsystem,
451 static struct device_operations device_ops = {
452 .read_resources = i82801gx_lpc_read_resources,
453 .set_resources = pci_dev_set_resources,
454 .enable_resources = i82801gx_lpc_enable_resources,
456 .scan_bus = scan_static_bus,
457 .enable = i82801gx_enable,
461 /* 82801GB/GR (ICH7/ICH7R) */
462 static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
464 .vendor = PCI_VENDOR_ID_INTEL,
468 /* 82801GBM/GU (ICH7-M/ICH7-U) */
469 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
471 .vendor = PCI_VENDOR_ID_INTEL,
475 /* 82801GHM (ICH7-M DH) */
476 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
478 .vendor = PCI_VENDOR_ID_INTEL,