src/southbridge/intel/i82801gx/i82801gx_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <pc80/isa-dma.h>
  27 #include <pc80/i8259.h>
  28 #include <arch/io.h>
  29 #include "i82801gx.h"
  30 #include "i82801gx_power.h"
  31
  32 #define NMI_OFF 0
  33
  34 #define ENABLE_ACPI_MODE_IN_COREBOOT    0
  35 #define TEST_SMM_FLASH_LOCKDOWN         0
  36
  37 typedef struct southbridge_intel_i82801gx_config config_t;
  38
  39 static void i82801gx_enable_apic(struct device *dev)
  40 {
  41         int i;
  42         u32 reg32;
  43         volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
  44         volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
  45
  46         /* Enable ACPI I/O and power management.
  47          * Set SCI IRQ to IRQ9
  48          */
  49         pci_write_config8(dev, ACPI_CNTL, 0x80);
  50
  51         *ioapic_index = 0;
  52         *ioapic_data = (1 << 25);
  53
  54         *ioapic_index = 0;
  55         reg32 = *ioapic_data;
  56         printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
  57         if (reg32 != (1 << 25))
  58                 die("APIC Error\n");
  59
  60         printk_spew("Dumping IOAPIC registers\n");
  61         for (i=0; i<3; i++) {
  62                 *ioapic_index = i;
  63                 printk_spew("  reg 0x%04x:", i);
  64                 reg32 = *ioapic_data;
  65                 printk_spew(" 0x%08x\n", reg32);
  66         }
  67
  68         *ioapic_index = 3; /* Select Boot Configuration register. */
  69         *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
  70 }
  71
  72 static void i82801gx_enable_serial_irqs(struct device *dev)
  73 {
  74         /* Set packet length and toggle silent mode bit for one frame. */
  75         pci_write_config8(dev, SERIRQ_CNTL,
  76                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
  77 }
  78
  79 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  80  * 0x00 - 0000 = Reserved
  81  * 0x01 - 0001 = Reserved
  82  * 0x02 - 0010 = Reserved
  83  * 0x03 - 0011 = IRQ3
  84  * 0x04 - 0100 = IRQ4
  85  * 0x05 - 0101 = IRQ5
  86  * 0x06 - 0110 = IRQ6
  87  * 0x07 - 0111 = IRQ7
  88  * 0x08 - 1000 = Reserved
  89  * 0x09 - 1001 = IRQ9
  90  * 0x0A - 1010 = IRQ10
  91  * 0x0B - 1011 = IRQ11
  92  * 0x0C - 1100 = IRQ12
  93  * 0x0D - 1101 = Reserved
  94  * 0x0E - 1110 = IRQ14
  95  * 0x0F - 1111 = IRQ15
  96  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  97  * 0x80 - The PIRQ is not routed.
  98  */
  99
 100 static void i82801gx_pirq_init(device_t dev)
 101 {
 102         device_t irq_dev;
 103         /* Get the chip configuration */
 104         config_t *config = dev->chip_info;
 105
 106         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
 107         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
 108         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
 109         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
 110
 111         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
 112         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
 113         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
 114         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 115
 116         /* Eric Biederman once said we should let the OS do this.
 117          * I am not so sure anymore he was right.
 118          */
 119
 120         for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 121                 u8 int_pin=0, int_line=0;
 122
 123                 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
 124                         continue;
 125
 126                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 127
 128                 switch (int_pin) {
 129                 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
 130                 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
 131                 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
 132                 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
 133                 }
 134
 135                 if (!int_line)
 136                         continue;
 137
 138                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 139         }
 140 }
 141
 142 static void i82801gx_gpi_routing(device_t dev)
 143 {
 144         /* Get the chip configuration */
 145         config_t *config = dev->chip_info;
 146         u32 reg32 = 0;
 147
 148         /* An array would be much nicer here, or some
 149          * other method of doing this.
 150          */
 151         reg32 |= (config->gpi0_routing & 0x03) << 0;
 152         reg32 |= (config->gpi1_routing & 0x03) << 2;
 153         reg32 |= (config->gpi2_routing & 0x03) << 4;
 154         reg32 |= (config->gpi3_routing & 0x03) << 6;
 155         reg32 |= (config->gpi4_routing & 0x03) << 8;
 156         reg32 |= (config->gpi5_routing & 0x03) << 10;
 157         reg32 |= (config->gpi6_routing & 0x03) << 12;
 158         reg32 |= (config->gpi7_routing & 0x03) << 14;
 159         reg32 |= (config->gpi8_routing & 0x03) << 16;
 160         reg32 |= (config->gpi9_routing & 0x03) << 18;
 161         reg32 |= (config->gpi10_routing & 0x03) << 20;
 162         reg32 |= (config->gpi11_routing & 0x03) << 22;
 163         reg32 |= (config->gpi12_routing & 0x03) << 24;
 164         reg32 |= (config->gpi13_routing & 0x03) << 26;
 165         reg32 |= (config->gpi14_routing & 0x03) << 28;
 166         reg32 |= (config->gpi15_routing & 0x03) << 30;
 167
 168         pci_write_config32(dev, 0xb8, reg32);
 169 }
 170
 171 extern u8 acpi_slp_type;
 172
 173 static void i82801gx_power_options(device_t dev)
 174 {
 175         u8 reg8;
 176         u16 reg16, pmbase;
 177         u32 reg32;
 178         char *state;
 179         /* Get the chip configuration */
 180         config_t *config = dev->chip_info;
 181
 182         int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 183         int nmi_option;
 184
 185         /* Which state do we want to goto after g3 (power restored)?
 186          * 0 == S0 Full On
 187          * 1 == S5 Soft Off
 188          *
 189          * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
 190          */
 191         if (get_option(&pwr_on, "power_on_after_fail") < 0)
 192                 pwr_on = MAINBOARD_POWER_ON;
 193
 194         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 195         reg8 &= 0xfe;
 196         switch (pwr_on) {
 197         case MAINBOARD_POWER_OFF:
 198                 reg8 |= 1;
 199                 state = "off";
 200                 break;
 201         case MAINBOARD_POWER_ON:
 202                 reg8 &= ~1;
 203                 state = "on";
 204                 break;
 205         case MAINBOARD_POWER_KEEP:
 206                 reg8 &= ~1;
 207                 state = "state keep";
 208                 break;
 209         default:
 210                 state = "undefined";
 211         }
 212
 213         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 214         reg8 &= ~(1 << 3);      /* minimum asssertion is 1 to 2 RTCCLK */
 215
 216         pci_write_config8(dev, GEN_PMCON_3, reg8);
 217         printk_info("Set power %s after power failure.\n", state);
 218
 219         /* Set up NMI on errors. */
 220         reg8 = inb(0x61);
 221         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 222         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 223         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 224         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 225         outb(reg8, 0x61);
 226
 227         reg8 = inb(0x70);
 228         nmi_option = NMI_OFF;
 229         get_option(&nmi_option, "nmi");
 230         if (nmi_option) {
 231                 printk_info ("NMI sources enabled.\n");
 232                 reg8 &= ~(1 << 7);      /* Set NMI. */
 233         } else {
 234                 printk_info ("NMI sources disabled.\n");
 235                 reg8 |= ( 1 << 7);      /* Can't mask NMI from PCI-E and NMI_NOW */
 236         }
 237         outb(reg8, 0x70);
 238
 239         /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
 240         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 241         reg16 &= ~((3 << 0) | (1 << 10));
 242         reg16 |= (1 << 3) | (1 << 5);
 243         reg16 |= (1 << 2);                      // CLKRUN_EN
 244 #if DEBUG_PERIODIC_SMIS
 245         /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
 246          * periodic SMIs.
 247          */
 248         reg16 |= (3 << 0); // Periodic SMI every 8s
 249 #endif
 250         pci_write_config16(dev, GEN_PMCON_1, reg16);
 251
 252         // Set the board's GPI routing.
 253         i82801gx_gpi_routing(dev);
 254
 255         pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 256
 257         outl(config->gpe0_en, pmbase + GPE0_EN);
 258         outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
 259
 260         /* Set up power management block and determine sleep mode */
 261         reg32 = inl(pmbase + 0x04); // PM1_CNT
 262 #if 0
 263 #if CONFIG_HAVE_ACPI_RESUME
 264         acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0;
 265         printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
 266                         reg32, acpi_slp_type);
 267 #endif
 268 #endif
 269         reg32 |= (1 << 1); // enable C3->C0 transition on bus master
 270         reg32 |= 1; // SCI_EN
 271         outl(reg32, pmbase + 0x04);
 272 }
 273
 274 static void i82801gx_configure_cstates(device_t dev)
 275 {
 276         u8 reg8;
 277
 278         reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
 279         reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
 280         pci_write_config8(dev, 0xa9, reg8);
 281
 282         // Set Deeper Sleep configuration to recommended values
 283         reg8 = pci_read_config8(dev, 0xaa);
 284         reg8 &= 0xf0;
 285         reg8 |= (2 << 2);       // Deeper Sleep to Stop CPU: 34-40us
 286         reg8 |= (2 << 0);       // Deeper Sleep to Sleep: 15us
 287         pci_write_config8(dev, 0xaa, reg8);
 288 }
 289
 290 static void i82801gx_rtc_init(struct device *dev)
 291 {
 292         u8 reg8;
 293         int rtc_failed;
 294
 295         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 296         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 297         if (rtc_failed) {
 298                 reg8 &= ~RTC_BATTERY_DEAD;
 299                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 300         }
 301         printk_debug("rtc_failed = 0x%x\n", rtc_failed);
 302
 303         rtc_init(rtc_failed);
 304 }
 305
 306 static void enable_hpet(void)
 307 {
 308         u32 reg32;
 309
 310         /* Move HPET to default address 0xfed00000 and enable it */
 311         reg32 = RCBA32(0x3404);
 312         reg32 |= (1 << 7); // HPET Address Enable
 313         reg32 &= ~(3 << 0);
 314         RCBA32(0x3404) = reg32;
 315 }
 316
 317 static void enable_clock_gating(void)
 318 {
 319         u32 reg32;
 320
 321         /* Enable Clock Gating for most devices */
 322         reg32 = RCBA32(0x341c);
 323         reg32 |= (1 << 31);     // LPC clock gating
 324         reg32 |= (1 << 30);     // PATA clock gating
 325         // SATA clock gating
 326         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 327         reg32 |= (1 << 23);     // AC97 clock gating
 328         reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
 329         reg32 |= (1 << 3) | (1 << 1);   // DMI clock gating
 330         reg32 |= (1 << 2);      // PCIe clock gating;
 331         RCBA32(0x341c) = reg32;
 332 }
 333
 334 #if CONFIG_HAVE_SMI_HANDLER
 335 static void i82801gx_lock_smm(struct device *dev)
 336 {
 337         void smm_lock(void);
 338 #if TEST_SMM_FLASH_LOCKDOWN
 339         u8 reg8;
 340 #endif
 341
 342 #if ENABLE_ACPI_MODE_IN_COREBOOT
 343         printk_debug("Enabling ACPI via APMC:\n");
 344         outb(0xe1, 0xb2); // Enable ACPI mode
 345         printk_debug("done.\n");
 346 #else
 347         printk_debug("Disabling ACPI via APMC:\n");
 348         outb(0x1e, 0xb2); // Disable ACPI mode
 349         printk_debug("done.\n");
 350 #endif
 351         /* Don't allow evil boot loaders, kernels, or
 352          * userspace applications to deceive us:
 353          */
 354         smm_lock();
 355
 356 #if TEST_SMM_FLASH_LOCKDOWN
 357         /* Now try this: */
 358         printk_debug("Locking BIOS to RO... ");
 359         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 360         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 361                         (reg8&1)?"rw":"ro");
 362         reg8 &= ~(1 << 0);                      /* clear BIOSWE */
 363         pci_write_config8(dev, 0xdc, reg8);
 364         reg8 |= (1 << 1);                       /* set BLE */
 365         pci_write_config8(dev, 0xdc, reg8);
 366         printk_debug("ok.\n");
 367         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 368         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 369                         (reg8&1)?"rw":"ro");
 370
 371         printk_debug("Writing:\n");
 372         *(volatile u8 *)0xfff00000 = 0x00;
 373         printk_debug("Testing:\n");
 374         reg8 |= (1 << 0);                       /* set BIOSWE */
 375         pci_write_config8(dev, 0xdc, reg8);
 376
 377         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 378         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 379                         (reg8&1)?"rw":"ro");
 380         printk_debug("Done.\n");
 381 #endif
 382 }
 383 #endif
 384
 385 #define SPIBASE 0x3020
 386 static void i82801gx_spi_init(void)
 387 {
 388         u16 spicontrol;
 389
 390         spicontrol = RCBA16(SPIBASE + 2);
 391         spicontrol &= ~(1 << 0); // SPI Access Request
 392         RCBA16(SPIBASE + 2) = spicontrol;
 393 }
 394
 395 static void i82801gx_fixups(void)
 396 {
 397         /* This needs to happen after PCI enumeration */
 398         RCBA32(0x1d40) |= 1;
 399 }
 400
 401 static void lpc_init(struct device *dev)
 402 {
 403         printk_debug("i82801gx: lpc_init\n");
 404
 405         /* Set the value for PCI command register. */
 406         pci_write_config16(dev, PCI_COMMAND, 0x000f);
 407
 408         /* IO APIC initialization. */
 409         i82801gx_enable_apic(dev);
 410
 411         i82801gx_enable_serial_irqs(dev);
 412
 413         /* Setup the PIRQ. */
 414         i82801gx_pirq_init(dev);
 415
 416         /* Setup power options. */
 417         i82801gx_power_options(dev);
 418
 419         /* Configure Cx state registers */
 420         i82801gx_configure_cstates(dev);
 421
 422         /* Set the state of the GPIO lines. */
 423         //gpio_init(dev);
 424
 425         /* Initialize the real time clock. */
 426         i82801gx_rtc_init(dev);
 427
 428         /* Initialize ISA DMA. */
 429         isa_dma_init();
 430
 431         /* Initialize the High Precision Event Timers, if present. */
 432         enable_hpet();
 433
 434         /* Initialize Clock Gating */
 435         enable_clock_gating();
 436
 437         setup_i8259();
 438
 439         /* The OS should do this? */
 440         // i8259_configure_irq_trigger(9, 1);
 441
 442 #if CONFIG_HAVE_SMI_HANDLER
 443         i82801gx_lock_smm(dev);
 444 #endif
 445
 446         i82801gx_spi_init();
 447
 448         i82801gx_fixups();
 449 }
 450
 451 static void i82801gx_lpc_read_resources(device_t dev)
 452 {
 453         struct resource *res;
 454
 455         /* Get the normal PCI resources of this device. */
 456         pci_dev_read_resources(dev);
 457
 458         /* Add an extra subtractive resource for both memory and I/O. */
 459         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 460         res->base = 0;
 461         res->size = 0x1000;
 462         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 463                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 464
 465         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 466         res->base = 0xff800000;
 467         res->size = 0x00800000; /* 8 MB for flash */
 468         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 469                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 470
 471         res = new_resource(dev, 3); /* IOAPIC */
 472         res->base = 0xfec00000;
 473         res->size = 0x00001000;
 474         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 475 }
 476
 477 static void i82801gx_lpc_enable_resources(device_t dev)
 478 {
 479         pci_dev_enable_resources(dev);
 480         enable_childrens_resources(dev);
 481 }
 482
 483 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 484 {
 485         if (!vendor || !device) {
 486                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 487                                 pci_read_config32(dev, PCI_VENDOR_ID));
 488         } else {
 489                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 490                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 491         }
 492 }
 493
 494 static struct pci_operations pci_ops = {
 495         .set_subsystem = set_subsystem,
 496 };
 497
 498 static struct device_operations device_ops = {
 499         .read_resources         = i82801gx_lpc_read_resources,
 500         .set_resources          = pci_dev_set_resources,
 501         .enable_resources       = i82801gx_lpc_enable_resources,
 502         .init                   = lpc_init,
 503         .scan_bus               = scan_static_bus,
 504         .enable                 = i82801gx_enable,
 505         .ops_pci                = &pci_ops,
 506 };
 507
 508 /* 82801GH (ICH7 DH) */
 509 static const struct pci_driver ich7_dh_lpc __pci_driver = {
 510         .ops    = &device_ops,
 511         .vendor = PCI_VENDOR_ID_INTEL,
 512         .device = 0x27b0,
 513 };
 514
 515 /* 82801GB/GR (ICH7/ICH7R) */
 516 static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
 517         .ops    = &device_ops,
 518         .vendor = PCI_VENDOR_ID_INTEL,
 519         .device = 0x27b8,
 520 };
 521
 522 /* 82801GBM/GU (ICH7-M/ICH7-U) */
 523 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
 524         .ops    = &device_ops,
 525         .vendor = PCI_VENDOR_ID_INTEL,
 526         .device = 0x27b9,
 527 };
 528
 529 /* 82801GHM (ICH7-M DH) */
 530 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
 531         .ops    = &device_ops,
 532         .vendor = PCI_VENDOR_ID_INTEL,
 533         .device = 0x27bd,
 534 };