src/southbridge/intel/i82801gx/i82801gx_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <pc80/isa-dma.h>
  27 #include <pc80/i8259.h>
  28 #include <arch/io.h>
  29 #include "i82801gx.h"
  30
  31 #include "../../../northbridge/intel/i945/ich7.h"
  32
  33 #define MAINBOARD_POWER_OFF 0
  34 #define MAINBOARD_POWER_ON  1
  35
  36 #ifndef MAINBOARD_POWER_ON_AFTER_FAIL
  37 #define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
  38 #endif
  39
  40 #define NMI_OFF 0
  41
  42 typedef struct southbridge_intel_i82801gx_config config_t;
  43
  44 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  45  * 0x00 - 0000 = Reserved
  46  * 0x01 - 0001 = Reserved
  47  * 0x02 - 0010 = Reserved
  48  * 0x03 - 0011 = IRQ3
  49  * 0x04 - 0100 = IRQ4
  50  * 0x05 - 0101 = IRQ5
  51  * 0x06 - 0110 = IRQ6
  52  * 0x07 - 0111 = IRQ7
  53  * 0x08 - 1000 = Reserved
  54  * 0x09 - 1001 = IRQ9
  55  * 0x0A - 1010 = IRQ10
  56  * 0x0B - 1011 = IRQ11
  57  * 0x0C - 1100 = IRQ12
  58  * 0x0D - 1101 = Reserved
  59  * 0x0E - 1110 = IRQ14
  60  * 0x0F - 1111 = IRQ15
  61  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  62  * 0x80 - The PIRQ is not routed.
  63  */
  64
  65 #define PIRQA 0x03
  66 #define PIRQB 0x05
  67 #define PIRQC 0x06
  68 #define PIRQD 0x07
  69 #define PIRQE 0x09
  70 #define PIRQF 0x0A
  71 #define PIRQG 0x0B
  72 #define PIRQH 0x0C
  73
  74 static void i82801gx_enable_apic(struct device *dev)
  75 {
  76         int i;
  77         u32 reg32;
  78         volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
  79         volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
  80
  81         /* Enable ACPI I/O and power management. */
  82         pci_write_config8(dev, ACPI_CNTL, 0x80);
  83
  84         *ioapic_index = 0;
  85         *ioapic_data = (1 << 25);
  86
  87         *ioapic_index = 0;
  88         reg32 = *ioapic_data;
  89         printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
  90         if (reg32 != (1 << 25))
  91                 die("APIC Error\n");
  92
  93         printk_spew("Dumping IOAPIC registers\n");
  94         for (i=0; i<3; i++) {
  95                 *ioapic_index = i;
  96                 printk_spew("  reg 0x%04x:", i);
  97                 reg32 = *ioapic_data;
  98                 printk_spew(" 0x%08x\n", reg32);
  99         }
 100
 101         *ioapic_index = 3; /* Select Boot Configuration register. */
 102         *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 103 }
 104
 105 static void i82801gx_enable_serial_irqs(struct device *dev)
 106 {
 107         /* Set packet length and toggle silent mode bit for one frame. */
 108         pci_write_config8(dev, SERIRQ_CNTL,
 109                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 110 }
 111
 112 static void i82801gx_pirq_init(device_t dev)
 113 {
 114         device_t irq_dev;
 115         /* Get the chip configuration */
 116         config_t *config = dev->chip_info;
 117
 118         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
 119         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
 120         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
 121         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
 122
 123         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
 124         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
 125         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
 126         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 127
 128         /* Eric Biederman once said we should let the OS do this.
 129          * I am not so sure anymore he was right.
 130          */
 131
 132         for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 133                 u8 int_pin=0, int_line=0;
 134
 135                 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
 136                         continue;
 137
 138                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 139
 140                 switch (int_pin) {
 141                 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
 142                 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
 143                 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
 144                 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
 145                 }
 146
 147                 if (!int_line)
 148                         continue;
 149
 150                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 151         }
 152 }
 153
 154 static void i82801gx_power_options(device_t dev)
 155 {
 156         u8 reg8;
 157         u16 reg16;
 158
 159         int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 160         int nmi_option;
 161
 162         /* Which state do we want to goto after g3 (power restored)?
 163          * 0 == S0 Full On
 164          * 1 == S5 Soft Off
 165          */
 166         get_option(&pwr_on, "power_on_after_fail");
 167         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 168         reg8 &= 0xfe;
 169         if (pwr_on) {
 170                 reg8 &= ~1;
 171         } else {
 172                 reg8 |= 1;
 173         }
 174         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 175
 176         pci_write_config8(dev, GEN_PMCON_3, reg8);
 177         printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
 178
 179         /* Set up NMI on errors. */
 180         reg8 = inb(0x61);
 181         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 182         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 183         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 184         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 185         outb(reg8, 0x61);
 186
 187         reg8 = inb(0x70);
 188         nmi_option = NMI_OFF;
 189         get_option(&nmi_option, "nmi");
 190         if (nmi_option) {
 191                 printk_info ("NMI sources enabled.\n");
 192                 reg8 &= ~(1 << 7);      /* Set NMI. */
 193         } else {
 194                 printk_info ("NMI sources disabled.\n");
 195                 reg8 |= ( 1 << 7);      /* Can't mask NMI from PCI-E and NMI_NOW */
 196         }
 197         outb(reg8, 0x70);
 198
 199         // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
 200         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 201         reg16 &= ~3;
 202         reg16 |= (1 << 3) | (1 << 5) | (1 << 10);
 203         pci_write_config16(dev, GEN_PMCON_1, reg16);
 204
 205         // Set GPIO13 to SCI (?)
 206         // This might be board specific
 207         pci_write_config32(dev, 0xb8, 0x08000000);
 208 }
 209
 210 void i82801gx_rtc_init(struct device *dev)
 211 {
 212         u8 reg8;
 213         u32 reg32;
 214         int rtc_failed;
 215
 216         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 217         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 218         if (rtc_failed) {
 219                 reg8 &= ~RTC_BATTERY_DEAD;
 220                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 221         }
 222         printk_debug("rtc_failed = 0x%x\n", rtc_failed);
 223
 224         rtc_init(rtc_failed);
 225 }
 226
 227 static void enable_hpet(struct device *dev)
 228 {
 229         /* TODO */
 230 }
 231
 232
 233 #if HAVE_SMI_HANDLER
 234 static void i82801gx_lock_smm(struct device *dev)
 235 {
 236         void smm_lock(void);
 237         u8 reg8;
 238
 239 #if ENABLE_ACPI_MODE_IN_COREBOOT
 240         printk_debug("Enabling ACPI via APMC:\n");
 241         outb(0xe1, 0xb2); // Enable ACPI mode
 242         printk_debug("done.\n");
 243 #else
 244         printk_debug("Disabling ACPI via APMC:\n");
 245         outb(0x1e, 0xb2); // Disable ACPI mode
 246         printk_debug("done.\n");
 247 #endif
 248         /* Don't allow evil boot loaders, kernels, or
 249          * userspace applications to deceive us:
 250          */
 251         smm_lock();
 252
 253 #if TEST_SMM_FLASH_LOCKDOWN
 254         /* Now try this: */
 255         printk_debug("Locking BIOS to RO... ");
 256         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 257         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 258                         (reg8&1)?"rw":"ro");
 259         reg8 &= ~(1 << 0);                      /* clear BIOSWE */
 260         pci_write_config8(dev, 0xdc, reg8);
 261         reg8 |= (1 << 1);                       /* set BLE */
 262         pci_write_config8(dev, 0xdc, reg8);
 263         printk_debug("ok.\n");
 264         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 265         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 266                         (reg8&1)?"rw":"ro");
 267
 268         printk_debug("Writing:\n");
 269         *(volatile u8 *)0xfff00000 = 0x00;
 270         printk_debug("Testing:\n");
 271         reg8 |= (1 << 0);                       /* set BIOSWE */
 272         pci_write_config8(dev, 0xdc, reg8);
 273
 274         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 275         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 276                         (reg8&1)?"rw":"ro");
 277         printk_debug("Done.\n");
 278 #endif
 279 }
 280 #endif
 281
 282 static void lpc_init(struct device *dev)
 283 {
 284         printk_debug("i82801gx: lpc_init\n");
 285
 286         /* Set the value for PCI command register. */
 287         pci_write_config16(dev, PCI_COMMAND, 0x000f);
 288
 289         /* IO APIC initialization. */
 290         i82801gx_enable_apic(dev);
 291
 292         i82801gx_enable_serial_irqs(dev);
 293
 294         /* Setup the PIRQ. */
 295         i82801gx_pirq_init(dev);
 296
 297         /* Setup power options. */
 298         i82801gx_power_options(dev);
 299
 300         /* Set the state of the GPIO lines. */
 301         //gpio_init(dev);
 302
 303         /* Initialize the real time clock. */
 304         i82801gx_rtc_init(dev);
 305
 306         /* Initialize ISA DMA. */
 307         isa_dma_init();
 308
 309         /* Initialize the High Precision Event Timers, if present. */
 310         enable_hpet(dev);
 311
 312         setup_i8259();
 313
 314 #if HAVE_SMI_HANDLER
 315         i82801gx_lock_smm(dev);
 316 #endif
 317 }
 318
 319 static void i82801gx_lpc_read_resources(device_t dev)
 320 {
 321         struct resource *res;
 322
 323         /* Get the normal PCI resources of this device. */
 324         pci_dev_read_resources(dev);
 325
 326         /* Add an extra subtractive resource for both memory and I/O. */
 327         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 328         res->flags =
 329             IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 330
 331         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 332         res->flags =
 333             IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 334 }
 335
 336 static void i82801gx_lpc_enable_resources(device_t dev)
 337 {
 338         pci_dev_enable_resources(dev);
 339         enable_childrens_resources(dev);
 340 }
 341
 342 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 343 {
 344         printk_debug("Setting LPC bridge subsystem ID\n");
 345         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 346                         pci_read_config32(dev, 0));
 347 }
 348
 349 static struct pci_operations pci_ops = {
 350         .set_subsystem = set_subsystem,
 351 };
 352
 353 static struct device_operations device_ops = {
 354         .read_resources         = i82801gx_lpc_read_resources,
 355         .set_resources          = pci_dev_set_resources,
 356         .enable_resources       = i82801gx_lpc_enable_resources,
 357         .init                   = lpc_init,
 358         .scan_bus               = scan_static_bus,
 359         .enable                 = i82801gx_enable,
 360         .ops_pci                = &pci_ops,
 361 };
 362
 363 /* 82801GB/GR (ICH7/ICH7R) */
 364 static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
 365         .ops    = &device_ops,
 366         .vendor = PCI_VENDOR_ID_INTEL,
 367         .device = 0x27b8,
 368 };
 369
 370 /* 82801GBM/GU (ICH7-M/ICH7-U) */
 371 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
 372         .ops    = &device_ops,
 373         .vendor = PCI_VENDOR_ID_INTEL,
 374         .device = 0x27b9,
 375 };
 376
 377 /* 82801GHM (ICH7-M DH) */
 378 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
 379         .ops    = &device_ops,
 380         .vendor = PCI_VENDOR_ID_INTEL,
 381         .device = 0x27bd,
 382 };