src/southbridge/intel/i82801gx/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
  22 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
  23
  24 struct southbridge_intel_i82801gx_config {
  25         /**
  26          * Interrupt Routing configuration
  27          * If bit7 is 1, the interrupt is disabled.
  28          */
  29         uint8_t pirqa_routing;
  30         uint8_t pirqb_routing;
  31         uint8_t pirqc_routing;
  32         uint8_t pirqd_routing;
  33         uint8_t pirqe_routing;
  34         uint8_t pirqf_routing;
  35         uint8_t pirqg_routing;
  36         uint8_t pirqh_routing;
  37
  38         /**
  39          * GPI Routing configuration
  40          *
  41          * Only the lower two bits have a meaning:
  42          * 00: No effect
  43          * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  44          * 10: SCI (if corresponding GPIO_EN bit is also set)
  45          * 11: reserved
  46          */
  47         uint8_t gpi0_routing;
  48         uint8_t gpi1_routing;
  49         uint8_t gpi2_routing;
  50         uint8_t gpi3_routing;
  51         uint8_t gpi4_routing;
  52         uint8_t gpi5_routing;
  53         uint8_t gpi6_routing;
  54         uint8_t gpi7_routing;
  55         uint8_t gpi8_routing;
  56         uint8_t gpi9_routing;
  57         uint8_t gpi10_routing;
  58         uint8_t gpi11_routing;
  59         uint8_t gpi12_routing;
  60         uint8_t gpi13_routing;
  61         uint8_t gpi14_routing;
  62         uint8_t gpi15_routing;
  63
  64         uint32_t gpe0_en;
  65         uint16_t alt_gp_smi_en;
  66
  67         /* IDE configuration */
  68         uint32_t ide_legacy_combined;
  69         uint32_t ide_enable_primary;
  70         uint32_t ide_enable_secondary;
  71         uint32_t sata_ahci;
  72 };
  73
  74 extern struct chip_operations southbridge_intel_i82801gx_ops;
  75
  76 #endif                          /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */