2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
22 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
24 struct southbridge_intel_i82801gx_config {
25 /* LPC configuration */
26 uint8_t pirqa_routing;
27 uint8_t pirqb_routing;
28 uint8_t pirqc_routing;
29 uint8_t pirqd_routing;
30 uint8_t pirqe_routing;
31 uint8_t pirqf_routing;
32 uint8_t pirqg_routing;
33 uint8_t pirqh_routing;
35 /* IDE configuration */
36 uint32_t ide_legacy_combined;
37 uint32_t ide_enable_primary;
38 uint32_t ide_enable_secondary;
41 /* Azalia Configuration */
42 unsigned long hda_viddid;
45 extern struct chip_operations southbridge_intel_i82801gx_ops;
47 #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */