src/southbridge/intel/i82801gx/acpi/ich7.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 /* Intel i82801G support
  23  */
  24
  25 Scope(\)
  26 {
  27         // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
  28
  29         OperationRegion(IO_T, SystemIO, 0x800, 0x10)
  30         Field(IO_T, ByteAcc, NoLock, Preserve)
  31         {
  32                 Offset(0x8),
  33                 TRP0, 8         // IO-Trap at 0x808
  34         }
  35
  36         // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
  37         // this doesn't work as ACPI initializes regions and packages first, devices second.
  38         // use dynamic operation region? if so, how? XXX
  39         //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)
  40         OperationRegion(PMIO, SystemIO, 0x500, 0x80)
  41         Field(PMIO, ByteAcc, NoLock, Preserve)
  42         {
  43                 Offset(0x42),   // General Purpose Control
  44                 , 1,            // skip 1 bit
  45                 GPEC, 1,        // TCO status
  46                 , 9,            // skip 9 more bits
  47                 SCIS, 1,        // TCO DMI status
  48                 , 6             // To the end of the word
  49         }
  50
  51         // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
  52         OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)
  53         Field(GPIO, ByteAcc, NoLock, Preserve)
  54         {
  55                 Offset(0x00),   // GPIO Use Select
  56                 GU00, 8,
  57                 GU01, 8,
  58                 GU02, 8,
  59                 GU03, 8,
  60                 Offset(0x04),   // GPIO IO Select
  61                 GIO0, 8,
  62                 GIO1, 8,
  63                 GIO2, 8,
  64                 GIO3, 8,
  65                 Offset(0x0c),   // GPIO Level
  66                 GL00, 8,
  67                 GL01, 8,
  68                 , 3,
  69                 GP27, 1,        // SATA_PWR_EN #0
  70                 GP28, 1,        // SATA_PWR_EN #1
  71                 , 3,
  72                 Offset(0x18),   // GPIO Blink
  73                 GB00, 8,
  74                 GB01, 8,
  75                 GB02, 8,
  76                 GB03, 8,
  77                 Offset(0x2c),   // GPIO Invert
  78                 GIV0, 8,
  79                 GIV1, 8,
  80                 GIV2, 8,
  81                 GIV3, 8,
  82                 Offset(0x30),   // GPIO Use Select 2
  83                 GU04, 8,
  84                 GU05, 8,
  85                 GU06, 8,
  86                 GU07, 8,
  87                 Offset(0x34),   // GPIO IO Select 2
  88                 GIO4, 8,
  89                 GIO5, 8,
  90                 GIO6, 8,
  91                 GIO7, 8,
  92                 Offset(0x38),   // GPIO Level 2
  93                 , 5,
  94                 GP37, 1,        // PATA_PWR_EN
  95                 GP38, 1,        // Battery / Power (?)
  96                 GP39, 1,        // ??
  97                 GL05, 8,
  98                 GL06, 8,
  99                 GL07, 8
 100         }
 101
 102
 103         // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
 104         OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)
 105         Field(RCRB, DWordAcc, Lock, Preserve)
 106         {
 107                 Offset(0x0000), // Backbone
 108                 Offset(0x1000), // Chipset
 109                 Offset(0x3000), // Legacy Configuration Registers
 110                 Offset(0x3404), // High Performance Timer Configuration
 111                 HPAS, 2,        // Address Select
 112                 , 5,
 113                 HPTE, 1,        // Address Enable
 114                 Offset(0x3418), // FD (Function Disable)
 115                 , 1,            // Reserved
 116                 PATD, 1,        // PATA disable
 117                 SATD, 1,        // SATA disable
 118                 SMBD, 1,        // SMBUS disable
 119                 HDAD, 1,        // Azalia disable
 120                 A97D, 1,        // AC'97 disable
 121                 M97D, 1,        // AC'97 disable
 122                 ILND, 1,        // Internal LAN disable
 123                 US1D, 1,        // UHCI #1 disable
 124                 US2D, 1,        // UHCI #2 disable
 125                 US3D, 1,        // UHCI #3 disable
 126                 US4D, 1,        // UHCI #4 disable
 127                 , 2,            // Reserved
 128                 LPBD, 1,        // LPC bridge disable
 129                 EHCD, 1,        // EHCI disable
 130                 Offset(0x341a), // FD Root Ports
 131                 RP1D, 1,        // Root Port 1 disable
 132                 RP2D, 1,        // Root Port 2 disable
 133                 RP3D, 1,        // Root Port 3 disable
 134                 RP4D, 1,        // Root Port 4 disable
 135                 RP5D, 1,        // Root Port 5 disable
 136                 RP6D, 1         // Root Port 6 disable
 137         }
 138
 139 }
 140
 141 // 0:1b.0 High Definition Audio (Azalia)
 142 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl")
 143
 144 // PCI Express Ports
 145 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl")
 146
 147 // USB
 148 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl")
 149
 150 // PCI Bridge
 151 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl")
 152
 153 // AC97 Audio and Modem
 154 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl")
 155
 156 // LPC Bridge
 157 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl")
 158
 159 // PATA
 160 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl")
 161
 162 // SATA
 163 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl")
 164
 165 // SMBus
 166 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl")
 167
 168