2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2004 SuSE Linux AG
6 * Copyright (C) 2004 Tyan Computer
7 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <device/pci_ops.h>
29 #include <pc80/mc146818rtc.h>
30 #include <pc80/isa-dma.h>
36 typedef struct southbridge_intel_i82801dx_config config_t;
38 static void i82801dx_enable_ioapic(struct device *dev)
41 volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
42 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
44 /* Set ACPI base address (I/O space). */
45 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
47 /* Enable ACPI I/O and power management. */
48 pci_write_config8(dev, ACPI_CNTL, 0x10);
50 reg32 = pci_read_config32(dev, GEN_CNTL);
51 reg32 |= (3 << 7); /* Enable IOAPIC */
52 reg32 |= (1 << 13); /* Coprocessor error enable */
53 reg32 |= (1 << 1); /* Delayed transaction enable */
54 reg32 |= (1 << 2); /* DMA collection buffer enable */
55 pci_write_config32(dev, GEN_CNTL, reg32);
56 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
59 *ioapic_data = (1 << 25);
63 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
64 if (reg32 != (1 << 25))
67 /* TODO: From i82801ca, needed/useful on other ICH? */
68 *ioapic_index = 3; /* Select Boot Configuration register. */
69 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
72 static void i82801dx_enable_serial_irqs(struct device *dev)
74 /* Set packet length and toggle silent mode bit. */
75 pci_write_config8(dev, SERIRQ_CNTL,
76 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
77 pci_write_config8(dev, SERIRQ_CNTL,
78 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
81 static void i82801dx_pirq_init(device_t dev)
83 /* Get the chip configuration */
84 config_t *config = dev->chip_info;
86 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
87 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
88 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
89 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
90 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
91 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
92 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
93 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
97 static void i82801dx_power_options(device_t dev)
103 /* power after power fail */
104 /* FIXME this doesn't work! */
105 /* Which state do we want to goto after g3 (power restored)?
109 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
110 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
112 /* Set up NMI on errors. */
114 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
115 byte &= ~(1 << 2); /* PCI SERR# Enable */
119 nmi_option = NMI_OFF;
120 get_option(&nmi_option, "nmi");
122 byte &= ~(1 << 7); /* Set NMI. */
127 static void gpio_init(device_t dev)
129 /* This should be done in romstage.c already */
130 pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
131 pci_write_config8(dev, GPIO_CNTL, 0x10);
134 static void i82801dx_rtc_init(struct device *dev)
140 reg8 = pci_read_config8(dev, GEN_PMCON_3);
141 rtc_failed = reg8 & RTC_BATTERY_DEAD;
143 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
144 pci_write_config8(dev, GEN_PMCON_3, reg8);
146 reg32 = pci_read_config32(dev, GEN_STS);
147 rtc_failed |= reg32 & (1 << 2);
148 rtc_init(rtc_failed);
150 /* Enable access to the upper 128 byte bank of CMOS RAM. */
151 pci_write_config8(dev, RTC_CONF, 0x04);
154 static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
159 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
161 for (i = 0; i < 8; i++) {
164 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
166 pci_write_config16(dev, PCI_DMA_CFG, reg16);
169 static void i82801dx_lpc_decode_en(device_t dev)
171 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
172 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
173 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
174 * We also need to set the value for LPC I/F Enables Register.
176 pci_write_config8(dev, COM_DEC, 0x10);
177 pci_write_config16(dev, LPC_EN, 0x300F);
180 /* ICH4 does not mention HPET in the docs, but
181 * all ICH3 and ICH4 do have HPETs built in.
183 static void enable_hpet(struct device *dev)
186 u32 code = (0 & 0x3);
188 reg32 = pci_read_config32(dev, GEN_CNTL);
189 reg32 |= (1 << 17); /* Enable HPET. */
191 * Bits [16:15] Memory Address Range
192 * 00 FED0_0000h - FED0_03FFh
193 * 01 FED0_1000h - FED0_13FFh
194 * 10 FED0_2000h - FED0_23FFh
195 * 11 FED0_3000h - FED0_33FFh
197 reg32 &= ~(3 << 15); /* Clear it */
198 reg32 |= (code << 15);
199 pci_write_config32(dev, GEN_CNTL, reg32);
201 printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
204 static void lpc_init(struct device *dev)
206 /* Set the value for PCI command register. */
207 pci_write_config16(dev, PCI_COMMAND, 0x000f);
209 /* IO APIC initialization. */
210 i82801dx_enable_ioapic(dev);
212 i82801dx_enable_serial_irqs(dev);
214 /* Setup the PIRQ. */
215 i82801dx_pirq_init(dev);
217 /* Setup power options. */
218 i82801dx_power_options(dev);
220 /* Set the state of the GPIO lines. */
223 /* Initialize the real time clock. */
224 i82801dx_rtc_init(dev);
227 i82801dx_lpc_route_dma(dev, 0xff);
229 /* Initialize ISA DMA. */
232 /* Setup decode ports and LPC I/F enables. */
233 i82801dx_lpc_decode_en(dev);
235 /* Initialize the High Precision Event Timers */
239 static void i82801dx_lpc_read_resources(device_t dev)
241 struct resource *res;
243 /* Get the normal PCI resources of this device. */
244 pci_dev_read_resources(dev);
246 /* Add an extra subtractive resource for both memory and I/O. */
247 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
250 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
251 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
253 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
254 res->base = 0xff800000;
255 res->size = 0x00800000; /* 8 MB for flash */
256 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
257 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
259 res = new_resource(dev, 3); /* IOAPIC */
260 res->base = 0xfec00000;
261 res->size = 0x00001000;
262 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
265 static void i82801dx_lpc_enable_resources(device_t dev)
267 pci_dev_enable_resources(dev);
268 enable_childrens_resources(dev);
271 static struct device_operations lpc_ops = {
272 .read_resources = i82801dx_lpc_read_resources,
273 .set_resources = pci_dev_set_resources,
274 .enable_resources = i82801dx_lpc_enable_resources,
276 .scan_bus = scan_static_bus,
277 .enable = i82801dx_enable,
281 static const struct pci_driver lpc_driver_db __pci_driver = {
283 .vendor = PCI_VENDOR_ID_INTEL,
284 .device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
288 static const struct pci_driver lpc_driver_dbm __pci_driver = {
290 .vendor = PCI_VENDOR_ID_INTEL,
291 .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,